An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor.
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1. A method of fabricating a semiconductor structure, comprising:
depositing a first barrier layer in a cavity in a dielectric layer, the cavity having a base and sidewalls, and the first barrier layer having a top horizontal surface;
depositing a second barrier layer over the first barrier layer, the second barrier layer having a top horizontal surface;
depositing a first metal layer on a base portion of the cavity, disposed over the second barrier layer;
removing the second barrier layer from sidewalls of the first barrier layer, resulting in the entire remaining top horizontal surface of the second barrier layer being parallel with the entire top horizontal surface of the first barrier layer; and
depositing a second metal layer in the cavity.
13. A method of fabricating a semiconductor structure, comprising:
depositing a first barrier layer in a cavity in a dielectric layer, the cavity having a base and sidewalls, and the first barrier layer having a top horizontal surface;
depositing a second barrier layer over the first barrier layer, the second barrier layer having a top horizontal surface;
depositing a first metal layer on a base portion of the cavity via radio frequency based physical vapor deposition, wherein the first metal layer is disposed over the second barrier layer;
removing the second barrier layer from sidewalls of the first barrier layer, resulting in the entire remaining top horizontal surface of the second barrier layer being parallel with the entire top horizontal surface of the first barrier layer; and
depositing a second metal layer in the cavity.
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1. Technical Field
The present invention relates generally to semiconductor fabrication, and more particularly, to an improved replacement metal gate of a field effect transistor and method of fabrication.
2. Related Art
Complimentary metal-oxide-silicon (CMOS) technology is used in many integrated circuits. CMOS technology utilizes n-channel metal-oxide-silicon field effect transistors (n-MOSFETs) often shortened to NFETs and p-channel metal-oxide-silicon field effect transistors (p-MOSFETs) often shortened to PFETs. Conventional NFETs and PFETs are well known in the art and comprise a source region and a drain region on opposite sides of a channel region formed in single-crystal silicon with a gate electrode formed on top of a gate dielectric layer which is itself formed on top of the channel region.
Some semiconductor devices, such as high performance processor devices, can include millions of field effect transistors. For such devices, decreasing transistors size, and thus increasing transistor density, has traditionally been a high priority in the semiconductor manufacturing industry. It is therefore desirable to have an improved field effect transistor and method of fabrication.
In general, embodiments of the invention provide an improved field effect transistor and method of fabrication. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor.
A first aspect of the present invention provides a method of fabricating a semiconductor structure, comprising: depositing a first barrier layer in a cavity in a dielectric layer, the cavity having a base and sidewalls; depositing a second barrier layer over the first barrier layer depositing a first metal layer in the cavity, disposed over the second barrier layer; removing the second barrier layer from the sidewalls of the cavity; and depositing a second metal layer in the cavity.
A second aspect of the present invention provides a method of fabricating a semiconductor structure comprising: depositing a first barrier layer in a cavity in a dielectric layer, the cavity having a base and sidewalls; depositing a second barrier layer over the first barrier layer; depositing a first metal layer in the cavity via radio frequency based physical vapor deposition, wherein the first metal layer is disposed over the second barrier layer; removing the second barrier layer from the sidewalls of the cavity; and depositing a second metal layer in the cavity.
A third aspect of the present invention provides a semiconductor structure, comprising: a first dielectric layer, comprising a cavity formed therein, the cavity having sidewalls and a base; a second dielectric layer disposed in the cavity; a first barrier layer disposed on the base of the cavity; a second barrier layer disposed on the first barrier layer; a first metal layer disposed in the cavity, on the second barrier layer; and a second metal layer disposed in the cavity, on the first metal layer.
The structure, operation, and advantages of the present invention will become further apparent upon consideration of the following description taken in conjunction with the accompanying figures. The figures are intended to be illustrative, not limiting.
Certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. In some cases, in particular pertaining to signals, a signal name may be oriented very close to a signal line without a lead line to refer to a particular signal, for illustrative clarity.
In some cases, reference numbers may not be explicitly referred to in the specification when a similar element has been introduced in a previous figure (FIG). Furthermore, for clarity, some reference numbers and/or features may be omitted in certain drawing figures (FIGS).
Exemplary embodiments will now be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. Described are methods and techniques used in forming an improved field effect transistor. Specifically, exemplary embodiments of the invention provide approaches for removing one or more sidewall barrier layers to avoid adversely affecting the threshold voltage of the transistor.
It will be appreciated that this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. For example, as used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Reference throughout this specification to “one embodiment,” “an embodiment,” “embodiments,” “exemplary embodiments,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” “in embodiments” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
The terms “overlying” or “atop”, “positioned on” or “positioned atop”, “underlying”, “beneath” or “below” mean that a first element, such as a first structure, e.g., a first layer, is present on a second element, such as a second structure, e.g. a second layer, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element.
In addition to metal layer 512, metal may also be deposited on the top of structure 500 (indicated by reference numbers 514 and 516). These metal regions will be removed in a subsequent planarization process. In some embodiments, first metal layer 512 is made of TiAl (titanium aluminum). One purpose of the first metal layer is to serve as a blocking layer to protect the base barrier regions during subsequent removal of sidewall barrier regions.
The second barrier layer 610B may be made of TaN. The first barrier layer 808 may be made of TiN. Barrier layers such as TiN and TaN are useful to provide isolation between the gate dielectric layer 806 and the second metal layer 818, which may be referred to as the “gate metal.” This is because the gate metal of an NFET is very reactive with oxygen. Without such barrier layers, a shift in threshold voltage (Vt) or leakage may occur. TiN and TaN have good properties as barriers for use with NFET metal gates. However, as the cavity width (gate length) L becomes smaller as the technology node size decreases, the effects of the work functions of TiN and TaN become significant contributors to the Vt of the transistor. As the gate length L decreases, the effect of the barrier on overall gate work function gets much bigger. Embodiments of the present invention remove the second barrier layer from the sidewalls (compare with 410S of
In various embodiments, design tools can be provided and configured to create the datasets used to pattern the semiconductor layers as described herein. For example, data sets can be created to generate photomasks used during lithography operations to pattern the layers for structures as described herein. Such design tools can include a collection of one or more modules and can also include hardware, software, or a combination thereof. Thus, for example, a tool can be a collection of one or more software modules, hardware modules, software/hardware modules or any combination or permutation thereof. As another example, a tool can be a computing device or other appliance on which software runs or in which hardware is implemented. As used herein, a module might be implemented utilizing any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, application-specific integrated circuits (ASIC), programmable logic arrays (PLA)s, logical components, software routines, or other mechanisms might be implemented to make up a module. In implementation, the various modules described herein might be implemented as discrete modules, or the functions and features described can be shared in part or in total among one or more modules. In other words, as would be apparent to one of ordinary skill in the art after reading this description, the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations. Even though various features or elements of functionality may be individually described or claimed as separate modules, one of ordinary skill in the art will understand that these features and functionality can be shared among one or more common software and hardware elements, and such description shall not require or imply that separate hardware or software components are used to implement such features or functionality.
It is apparent that there has been provided approaches for an improved field effect transistor and method of fabrication. While the invention has been particularly shown and described in conjunction with exemplary embodiments, it will be appreciated that variations and modifications will occur to those skilled in the art. For example, although the illustrative embodiments are described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events unless specifically stated. Some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the invention.
Park, Chanro, Kim, Hoon, Choi, Kisik
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