Double sidewall image transfer process

Abstract

Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

Description

TECHNICAL FIELD

The present disclosure relates to manufacture of semiconductor devices with fins. The present disclosure is particularly applicable to generating fins for a static random access memory (SRAM) bitcell for the 10 nanometer (nm) technology node and beyond.

BACKGROUND

In fabrication of semiconductor devices, particularly fabrication of SRAM bitcells, traditional methods utilize fins generated using a single sidewall image transfer (SIT) process. However, traditional single SIT methods may only generate fins having a fin pitch greater than 40 nm. Further, traditional SIT methods generate a constant fin pitch, resulting in an inefficient use of layout area.

A need therefore exists for methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device.

SUMMARY

An aspect of the present disclosure is a method of generating fins on a substrate by, inter alia, utilizing a first spacer on each side of a mandrel as a mandrel for a second spacer.

Another aspect of the present disclosure is a device having, inter alia, a first and second fin being separated by a first distance and a third fin being separated from the second fin by a second distance, different from the first distance.

Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.

According to the present disclosure, some technical effects may be achieved in part by a method including: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

Aspects include a method, wherein the first and second mandrels have first and second widths, respectively, the method further including providing the second mandrel on the hardmask at a distance from the first mandrel, the distance exceeding the first width, second width, or each of the first and second widths. Further aspects include a method, wherein the first spacers each have a third width being less than the distance, first width, second width, or a combination thereof. Additional aspects include etching, after removal of the first spacers, the hardmask using the second spacers as a mask. Some aspects include etching, after etching of the hardmask, a part of a layer of the substrate using the hardmask as a mask, a remaining part of the layer being first, second, third, fourth, fifth, sixth, seventh, and eighth fins, the second fin being between the first and third fin, the third fin being between the second and fourth fins, the fourth fin being between the third and fifth fins, the fifth fin being between the fourth and sixth fins, the sixth fin being between the fifth and seventh fins, and the seventh fin being between the sixth and eighth fins; and removing the hardmask and the second spacers. Further aspects include: forming, in the substrate, a first pull-down (PD) transistor, wherein the first fin is formed on the first PD transistor; forming, in the substrate, a first pass-gate (PG) transistor, wherein the first fin is formed on the first PG transistor; forming, in the substrate, a first pull-up (PU) transistor, wherein the second fin is formed on the first PU transistor; forming, in the substrate, a second PU transistor, wherein the third fin is formed on the second PU transistor; forming, in the substrate, a second PG transistor, wherein the fourth fin is formed on the second PG transistor; and forming, in the substrate, a second PD transistor, wherein the fourth fin is formed on the second PD transistor. Additional aspects include: forming, in the substrate, a first PD transistor, wherein the first and second fins are formed on the first PD transistor; forming, in the substrate, a first PG transistor, wherein the first and second fins are formed on the first PG transistor; forming, in the substrate, a first PU transistor, wherein the third fin is formed on the first PU transistor; forming, in the substrate, a second PU transistor, wherein the sixth fin is formed on the second PU transistor; forming, in the substrate, a second PG transistor, wherein the seventh and eighth fins are formed on the second PG transistor; and forming, in the substrate, a second PD transistor, wherein the seventh and eighth fins are formed on the second PD transistor. Some aspects include a method, wherein the fourth fin is formed on the first PU transistor and the fifth fin is formed on the second PU transistor.

Another aspect of the present disclosure is a device having: a substrate; a first fin in the substrate; a second fin in the substrate being separated from the first fin by a first distance; a third fin in the substrate being separated from the second fin by a second distance, and being separated from the first fin by the second fin, wherein the first and second distances are different; and a fourth fin in the substrate separated from the third fin by the first distance, the fourth fin being separated from the second fin by the third fin.

Aspects include a device, wherein the first distance is less than the second distance. Additional aspects include a device having: a fifth fin in the substrate separated from the fourth fin by a third distance, the fifth fin being separated from the third fin by the fourth fin; a sixth fin in the substrate separated from the fifth fin by the first distance, the sixth fin being separated from the fourth fin by the fifth fin; a seventh fin in the substrate separated from the sixth fin by the second distance, the seventh fin being separated from the fifth fin by the sixth fin; and an eighth fin in the substrate separated from the seventh fin by the first distance, and the eighth fin being separated from the sixth fin by the seventh fin. Further aspects include a device, wherein the first, second, and third distances are different. Some aspects include a device having: a first PD transistor, in the substrate, wherein the first fin is formed on the first PD transistor; a first PG transistor, in the substrate, wherein the first fin is formed on the first PG transistor; a first PU transistor, in the substrate, wherein the second fin is formed on the first PU transistor; a second PU transistor, in the substrate, wherein the third fin is formed on the second PU transistor; a second PG transistor, in the substrate, wherein the fourth fin is formed on the second PG transistor; and a second PD transistor, in the substrate, wherein the fourth fin is formed on the second PD transistor. Additional aspects include a device having: a first PD transistor, in the substrate, wherein the first, second, and third fins are formed on the first PD transistor; a first PG transistor, in the substrate, wherein the first and second fins are formed on the first PG transistor; a first PU transistor, in the substrate, wherein the fourth fin is formed on the first PU transistor; a second PU transistor, in the substrate, wherein the fifth fin is formed on the second PU transistor; a second PG transistor, in the substrate, wherein the seventh and eighth fins are formed on the second PG transistor; and a second PD transistor, in the substrate, wherein the sixth, seventh, and eighth fins are formed on the second PD transistor. Some aspects include a device having: a first PD transistor, in the substrate, wherein the first and second fins are formed on the first PD transistor; a first PG transistor, in the substrate, wherein the first and second fins are formed on the first PG transistor; a first PU transistor, in the substrate, wherein the third fin is formed on the first PU transistor; a second PU transistor, in the substrate, wherein the sixth fin is formed on the second PU transistor; a second PG transistor, in the substrate, wherein the seventh and eighth fins are formed on the second PG transistor; and a second PD transistor, in the substrate, wherein the seventh and eighth fins are formed on the second PD transistor. Further aspects include a device, wherein the fourth fin is formed on the first PU transistor and the fifth fin is formed on the second PU transistor.

Another aspect of the present disclosure is a method including: forming a hardmask on a substrate; providing a first mandrel having a first width on the hardmask; providing a second mandrel having a second width, different from the first width, on the hardmask at a first distance from the first mandrel, the first distance exceeding the first width; providing a first spacer on each side of each of the first and second mandrels, each of the first spacers having a third width being less than the first and second widths; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers, each of the second spacers having a fourth width being less the third width; removing the first spacers; etching, after removal of the first spacers, the hardmask using the second spacers as a mask; etching, after etching of the hardmask, a part of a layer of the substrate using the hardmask as a mask, a remaining part of the layer being first, second, third, fourth, fifth, sixth, seventh, and eighth fins, the second fin being between the first and third fin, the third fin being between the second and fourth fins, the fourth fin being between the third and fifth fins, the fifth fin being between the fourth and sixth fins, the sixth fin being between the fifth and seventh fins, and the seventh fin being between the sixth and eighth fins; and removing the hardmask and the second spacers.

Some aspects include: forming, in the substrate, a first PD transistor, wherein the first fin is formed on the first PD transistor; forming, in the substrate, a first PG transistor, wherein the first fin is formed on the first PG transistor; forming, in the substrate, a first PU transistor, wherein the second fin is formed on the first PU transistor; forming, in the substrate, a second PU transistor, wherein the third fin is formed on the second PU transistor; forming, in the substrate, a second PG transistor, wherein the fourth fin is formed on the second PG transistor; and forming, in the substrate, a second PD transistor, wherein the fourth fin is formed on the second PD transistor. Further aspects include: forming, in the substrate, a first PD transistor, wherein the first and second fins are formed on the first PD transistor; forming, in the substrate, a first PG transistor, wherein the first and second fins are formed on the first PG transistor; forming, in the substrate, a first PU transistor, wherein the third fin is formed on the first PU transistor; forming, in the substrate, a second PU transistor, wherein the sixth fin is formed on the second PU transistor; forming, in the substrate, a second PG transistor, wherein the seventh and eighth fins are formed on the second PG transistor; and forming, in the substrate, a second PD transistor, wherein the seventh and eighth fins are formed on the second PD transistor. Additional aspects include a method, wherein the fourth fin is formed on the first PU transistor and the fifth fin is formed on the second PU transistor.

Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

FIGS. 1 through 6 schematically illustrate a double SIT process for forming fins having variable pitch, in accordance with an exemplary embodiment; and

FIGS. 7A, 7B, 7C, and 7D schematically illustrate exemplary SRAM bitcells utilizing fins having a variable pitch of less than 40 nm, in accordance with exemplary embodiments.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”

The present disclosure addresses and solves the current problem of an inability to form fins on a substrate having a fin pitch less than 40 nm and/or having a variable pitch attendant upon forming semiconductor devices, particularly SRAM bitcells, using a conventional SIT process. In accordance with embodiments of the present disclosure, the problems are solved, for instance by, inter alia, utilizing a first spacer on each side of a mandrel as a mandrel for a second spacer. Further, aspects of the present disclosure enable a variable fin pitch by, for instance, adjusting the mandrel widths and spacing and the first spacer widths.

Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

Adverting to FIG. 1 in accordance with exemplary embodiments, a substrate 101, for example a bulk silicon substrate, is provided with a hardmask 103 having a first mandrel 105a and a second mandrel 105b. The mandrels 105a and 105b may be formed of amorphous silicon (a-Si) and have widths 107a and 107b, respectively, which may be identical or different. As shown, the mandrels 105a and 105b are separated by distance 109 from each other exceeding widths 107a and 107b of the mandrels 105a and 105b. The substrate 101, hardmask 103, and mandrels 105a and 105b may be formed using conventional front-end-of-line (FEOL) steps.

Adverting to FIG. 2, first spacers 201 having widths 203 are provided on sides of each of the mandrels 105a and 105b. The first spacers 201 may be a formed of nitride and have identical widths. As shown in FIG. 2, the first spacers 201 have widths 203 being less than widths 107a and 107b of the mandrels 105a and 105b, respectively.

As illustrated in FIG. 3, the mandrels 105a and 105b are removed and second spacers 301 are provided on sides of each of the first spacers 201. Adverting to FIG. 4, the first spacers 201 are removed and portions 401 of the hardmask 103 remain after the hardmask 103 is etched using the second spacers 301 as a mask. Next, as illustrated in FIG. 5, fins 501a through 501h are formed after etching using the remaining portion 401 of the hardmask 103 as a mask. As shown, fins 501a through 501h include the second fin 501b being between the first fin 501a and third fin 501c, the third fin 501c being between the second fin 501b and fourth fin 501d, the fourth fin 501d being between the third fin 501c and fifth fin 501e, the fifth fin 501e being between the fourth fin 501d and sixth fin 501f, the sixth fin 501f being between the fifth fin 501e and seventh fin 501h, and the seventh fin 501g being between the sixth fin 501f and eighth fin 501h. Fins 501a through 501h have a uniform thickness, but may have variable spacing.

FIG. 6 illustrates a resulting device 600 with the second spacers 301 and the hardmask 103, including portions 401, removed. As illustrated, fins 501a and 501b are separated by a first distance 601, fins 501b and 501c are separated by a second distance 603, and fins 501d and 501e are separated by a third distance 605. As shown, the first distance 601, second distance 603, and third distance 605 are different. A coupled fin's inter-spaces (e.g., second and third distances 603 and 605) are based on a width of mandrel (e.g., 105a) and a space between mandrels (e.g., 109). For instance, as a width of mandrels (e.g., 107a and 107b) increases, an inter-space 603 of resulting fins increases, while inter-space 605 decreases. Therefore, space 605 may be the same as, greater than, or less than space 603.

FIGS. 7A, 7B, 7C, and 7D schematically illustrate fins having variable pitch of less than 40 nm (e.g., 20 nm) on exemplary SRAM bitcells, in accordance with exemplary embodiments. FIGS. 7A, 7B, 7C, and 7D include fins 701a through 701h, PD transistors 703a through 703d, PG transistors 705a through 705d, and PU transistors 707a through 707d. Fins 701a through 701h may be generated in multiples of four (e.g., 4, 8, 12, etc.).

FIG. 7A illustrates an exemplary 1-1-1 SRAM configuration having fin 701a formed on PD transistor 703a and PG transistor 705a, fin 701b formed on PU transistor 707a, fin 701c formed PU transistor 707b, and fin 701d formed on PD transistor 703b and PG transistor 705b. Additional 1-1-1 SRAM bitcells may be formed on the same substrate (e.g., 101). For instance, FIG. 7A illustrates a second 1-1-1 SRAM having fin 701e formed on PD transistor 703c and PG transistor 705c, fin 701f formed on PU transistor 707c, fin 701g formed on PU transistor 707d, fin 701h formed on PD transistor 703d and PG transistor 705d. As noted before, generating fins (e.g., 501a through 501h, 701a through 701h) with a variable fin pitch enables efficient use of layout areas. For example, a device may require a first spacing 709 to allow for a particular layout (such as that illustrated in FIG. 7A) of PD transistors 703 and PU transistors 707, and a second spacing 711, larger than the first spacing 709, to allow for a specific layout of PU transistors 707. As such, the resulting device shown in FIG. 7A is configured to separate fins corresponding to PD transistors from fins corresponding to PU transistors by the first spacing 709, and separate fins corresponding to PU transistors from fins corresponding to other PU transistors by the second spacing 711. For instance, fin 701b being formed on PU transistor 707a may be separated by the first spacing 709 of 20 nm from fin 701a which is formed on PD transistor 703a. Similarly, fin 701b being formed on PU transistor 707a may be separated by the second spacing 711 of 30 nm from fin 701c which is formed on PU transistor 707b.

FIG. 7B illustrates an exemplary 1-2-2 SRAM configuration having fins 701a and 701b formed on PD transistor 703a and PG transistor 705a, fin 701c formed on PU transistor 707a, fin 701f formed on PU transistor 707b, and fins 701g and 701h formed on PD transistor 703b and PG transistor 705b. Additional 1-2-2 SRAM bitcells may be formed on the same substrate (not shown). As illustrated, the exemplary 1-2-2 SRAM has a first distance 713 of 30 nm, a second distance 715 of 44 nm and a third distance 717 of 24 nm. The exemplary 1-2-2 SRAM may be formed using the processes described with respect to FIGS. 1 through 6, for example, with a first mandrel (e.g., 105a) having a width (e.g., 107a) of 40 nm being separated by a distance (e.g., 109) of 120 nm from a second mandrel (e.g., 105b) having a width (e.g., 107b) of 90 nm, a first spacer (e.g., 201) having a width (e.g., 203) of 30 nm, and a second spacer (e.g., 301) having a width of 8 nm.

FIG. 7C illustrates an exemplary 2-2-2 SRAM configuration having fins 701a and 701b formed on PD transistor 703a and PG transistor 705a, fins 701c and 701d formed on PU transistor 707a, fins 701e and 701f formed on PU transistor 707b, and fins 701g and 701h formed on PD transistor 703b and PG transistor 705b. Additional 2-2-2 SRAM bitcells may be formed on the same substrate (not shown). As illustrated, the exemplary 2-2-2 SRAM has a first distance 713 of 20 nm, a second distance 715 of 44 nm and a third distance 717 of 44 nm. The exemplary 2-2-2 SRAM may be formed using the processes described with respect to FIGS. 1 through 6, for example, with a first mandrel (e.g., 105a) having a width (e.g., 107a) of 60 nm being separated by a distance (e.g., 109) of 100 nm from a second mandrel (e.g., 105b) having a width (e.g., 107b) of 90 nm, a first spacer (e.g., 201) having a width (e.g., 203) of 20 nm, and a second spacer (e.g., 301) having a width of 8 nm.

FIG. 7D illustrates an exemplary 1-2-3 SRAM configuration having fins 701a and 701b formed on PD transistor 703a and PG transistor 705a, fin 701c formed on PD transistor 703a, fin 701d formed on PU transistor 707a, fin 701e formed on PU transistor 707b, fin 701f formed on PD transistor 703b, and fins 701g and 701h formed on PD transistor 703b and PG transistor 705b. Additional 1-2-3 SRAM bitcells may be formed on the same substrate (not shown). As illustrated, the exemplary 1-2-3 SRAM has a first distance 713 of 40 nm, a second distance 715 of 30 nm and a third distance 717 of 44 nm. The exemplary 1-2-3 SRAM may be formed using the processes described with respect to FIGS. 1 through 6, for example, with a first mandrel (e.g., 105a) having a width (e.g., 107a) of 60 nm being separated by a distance (e.g., 109) of 126 nm from a second mandrel (e.g., 105b) having a width (e.g., 107b) of 90 nm, a first spacer (e.g., 201) having a width (e.g., 203) of 40 nm, and a second spacer (e.g., 301) having a width of 8 nm.

The embodiments of the present disclosure can achieve several technical effects, including formation of fins having a variable fin pitch less than 40 nm, thereby providing more efficient use of bitcell layout area. The present disclosure enjoys industrial applicability in any of various types of highly integrated semiconductor devices, particularly SRAM bitcells.

In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.

Claims

1. A method comprising:

forming a hardmask on a substrate;

providing first and second mandrels on the hardmask having first and second widths, respectively, wherein the first and second widths are different;

providing a first spacer on each side of each of the first and second mandrels;

removing the first and second mandrels;

providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers;

removing the first spacers;

etching, after removal of the first spacers, the hardmask using the second spacers as a mask; and

generating a plurality of fins by etching, after etching of the hardmask, a part of a layer of the substrate using the hardmask as a mask,

wherein the fins have a variable fin pitch less than 40 nm.

2. The method according to claim 1, the method further comprising:

providing the second mandrel on the hardmask at a distance from the first mandrel, the distance exceeding the first width, second width, or each of the first and second widths.

3. The method according to claim 2, wherein the first spacers each have a third width being less than the distance, first width, second width, or a combination thereof.

4. The method according to claim 1, further comprising:

removing the hardmask and the second spacers,

wherein the plurality of fins comprise first, second, third, fourth, fifth, sixth, seventh, and eighth fins, the second fin being between the first and third fin, the third fin being between the second and fourth fins, the fourth fin being between the third and fifth fins, the fifth fin being between the fourth and sixth fins, the sixth fin being between the fifth and seventh fins, and the seventh fin being between the sixth and eighth fins.

5. The method according to claim 4, comprising:

forming, in the substrate, a first pull-down (PD) transistor, wherein the first fin is formed on the first PD transistor;

forming, in the substrate, a first pass-gate (PG) transistor, wherein the first fin is formed on the first PG transistor;

forming, in the substrate, a first pull-up (PU) transistor, wherein the second fin is formed on the first PU transistor;

forming, in the substrate, a second PU transistor, wherein the third fin is formed on the second PU transistor;

forming, in the substrate, a second PG transistor, wherein the fourth fin is formed on the second PG transistor; and

forming, in the substrate, a second PD transistor, wherein the fourth fin is formed on the second PD transistor.

6. The method according to claim 4, comprising:

forming, in the substrate, a first PD transistor, wherein the first and second fins are formed on the first PD transistor;

forming, in the substrate, a first PG transistor, wherein the first and second fins are formed on the first PG transistor;

forming, in the substrate, a first PU transistor, wherein the third fin is formed on the first PU transistor;

forming, in the substrate, a second PU transistor, wherein the sixth fin is formed on the second PU transistor;

forming, in the substrate, a second PG transistor, wherein the seventh and eighth fins are formed on the second PG transistor; and

forming, in the substrate, a second PD transistor, wherein the seventh and eighth fins are formed on the second PD transistor.

7. The method according to claim 6, wherein the fourth fin is formed on the first PU transistor and the fifth fin is formed on the second PU transistor.

8. A method comprising:

forming a hardmask on a substrate;

providing a first mandrel having a first width on the hardmask;

providing a second mandrel having a second width, different from the first width, on the hardmask at a first distance from the first mandrel, the first distance exceeding the first width;

providing a first spacer on each side of each of the first and second mandrels, each of the first spacers having a third width being less than the first and second widths;

removing the first and second mandrels;

providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers, each of the second spacers having a fourth width being less the third width;

removing the first spacers;

etching, after removal of the first spacers, the hardmask using the second spacers as a mask;

etching, after etching of the hardmask, a part of a layer of the substrate using the hardmask as a mask, a remaining part of the layer being first, second, third, fourth, fifth, sixth, seventh, and eighth fins, the second fin being between the first and third fin, the third fin being between the second and fourth fins, the fourth fin being between the third and fifth fins, the fifth fin being between the fourth and sixth fins, the sixth fin being between the fifth and seventh fins, and the seventh fin being between the sixth and eighth fins; and

removing the hardmask and the second spacers,

wherein the fins have a variable fin pitch less than 40 nm.

9. The method according to claim 8, further comprising:

forming, in the substrate, a first pull-down (PD) transistor, wherein the first fin is formed on the first PD transistor;

forming, in the substrate, a first pass-gate (PG) transistor, wherein the first fin is formed on the first PG transistor;

forming, in the substrate, a first pull-up (PU) transistor, wherein the second fin is formed on the first PU transistor;

forming, in the substrate, a second PU transistor, wherein the third fin is formed on the second PU transistor;

forming, in the substrate, a second PG transistor, wherein the fourth fin is formed on the second PG transistor; and

forming, in the substrate, a second PD transistor, wherein the fourth fin is formed on the second PD transistor.

10. The method according to claim 8, further comprising:

forming, in the substrate, a first PD transistor, wherein the first and second fins are formed on the first PD transistor;

forming, in the substrate, a first PG transistor, wherein the first and second fins are formed on the first PG transistor;

forming, in the substrate, a first PU transistor, wherein the third fin is formed on the first PU transistor;

forming, in the substrate, a second PU transistor, wherein the sixth fin is formed on the second PU transistor;

forming, in the substrate, a second PG transistor, wherein the seventh and eighth fins are formed on the second PG transistor; and

forming, in the substrate, a second PD transistor, wherein the seventh and eighth fins are formed on the second PD transistor.

11. The method according to claim 10, wherein the fourth fin is formed on the first PU transistor and the fifth fin is formed on the second PU transistor.

12. A method comprising:

forming a hardmask on a substrate;

providing first and second mandrels on the hardmask having first and second widths, respectively, wherein the first and second widths are different;

providing a first spacer on each side of each of the first and second mandrels;

removing the first and second mandrels;

providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers;

removing the first spacers;

etching, after removal of the first spacers, the hardmask using the second spacers as a mask; and

generating a plurality of fins by etching, after etching of the hardmask, a part of a layer of the substrate using the hardmask as a mask,

wherein a first fin and a second fin of the plurality of fins are separated by a first distance, the second fin and a third fin of the plurality of fins are separated by a second distance, and the third fin and a fourth fin of the plurality of fins are separated by a third distance, the first distance, the second distance, and the third distance being different from each other.