memory devices, memory arrays, and methods of operation of memory arrays with segmentation. segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements.
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14. A memory array, comprising:
a block of variable resistance memory cells connected to a global access line by a segmentation element, and connected to a first biasing line by a first biasing device and to a second biasing line by a second biasing device;
wherein the first and second biasing lines are configured to receive a same voltage during an access operation.
20. A method of operating a memory, comprising:
biasing a two terminal segmentation element for selected cells of a selected block of the memory to turn the segmentation element on;
biasing a two terminal segmentation element for unselected cells of a selected block of the memory to turn the segmentation element off; and
biasing segmentation elements for unselected blocks of the memory to turn the segmentation elements off.
11. A memory device, comprising:
a group of memory cells, each cell connected in series between a local first access line and a respective one of a plurality of second access lines; and
a segmentation diode connected between the local first access line and a global first access line;
wherein the segmentation diode comprises a first segmentation diode and further comprising a second segmentation diode connected in parallel with the first segmentation diode between the local first access line and the global first access line.
19. A memory device, comprising:
a group of variable resistance memory cells connected to a local access line, wherein the local access line is connected to a global access line by a segmentation element;
a first biasing line;
a second biasing line;
a first biasing device connected between the first biasing line and the local access line; and
a second biasing device connected between the second biasing line and the local access line;
wherein the first and second biasing lines are configured to receive a same voltage during an access operation.
9. A memory device, comprising:
a group of memory cells, each cell connected in series between a local first access line and a respective one of a plurality of second access lines;
a segmentation diode connected between the local first access line and a global first access line;
a first biasing diode connected between a first biasing line and the local first access line; and
a second biasing diode connected between a second biasing line and the local first access line;
wherein the first and second biasing lines are configured to receive a same voltage during an access operation.
1. A memory device, comprising:
a group of memory cells, each cell connected in series between a local first access line and a respective one of a plurality of second access lines;
a segmentation element connected between the local first access line and a global first access line;
a first biasing line;
a second biasing line;
a first biasing device connected between the first biasing line and the local first access line; and
a second biasing device connected between the second biasing line and the local first access line;
wherein the first and second biasing lines are configured to receive a same voltage during an access operation.
2. The memory device of
5. The memory device of
8. The memory device of
10. The memory device of
15. The memory array of
a plurality of variable resistance memory cells at intersections of local access lines, each memory cell comprising a programmable element and a select device connected in series between its respective local access lines.
18. The memory array of
21. The method of
biasing lines to reverse bias select devices of unselected cells of the memory.
22. The method of
23. The method of
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The present embodiments relate generally to memory and a particular embodiment relates to variable resistance memory devices.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, flash drives, digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
Flash memory density has increased and cost per bit has decreased in recent years. To increase density, memory cell size and proximity to adjacent memory cells have been reduced. This can lead to problems with disturb conditions resulting from interaction between adjacent memory cells. Additionally, flash memory is still relatively slow when compared to other forms of memory (e.g., DRAM).
Variable resistance memory, such as resistive random access memory (RRAM), is a memory technology that provides a non-volatile memory function in a variable resistance memory cell. For example, a low resistance of the memory cell indicates one state while a high resistance indicates a second state. Examples of such variable resistance memory includes metal oxide, phase change (GST), nano-filament, stiction force, mechanical deformation, polymer, molecular, conductive bridge, and MRAM.
Because of the size of modern arrays, the amount of current from a large amount of cells connected to an access line, and leakage from cells, bit lines and word lines cannot span an entire length and width of a memory. Connected to in this context includes, but is not limited to, being electrically connected to, whether directly or indirectly through an intervening component or components. Therefore, bit line and word line segmentation is used as is shown in
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved memory array architecture.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments. In the drawings, like numerals describe substantially similar components throughout the several views. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense.
Cross point RRAM array cells are a two tier stack of components. Typically, an RRAM array cell comprises a programmable element (e.g., a variable resistive element) that is usually either over or under a select device. The variable resistive element changes states, and the different states represent a programmed cell and an erased cell. The select device is used for the purpose of selecting the particular cell of interest in the array. A cross point array is so named because the access lines, referred to as bit lines and word lines, of the array cross at 90 degree angles, for example, forming a compact efficient array having a small area. The bit lines and word lines are typically sized as small as equipment can make them, and the spacing between adjacent bit lines and between adjacent word lines is also typically as small. For the purposes of explanation, bit lines are shown in the figures in a vertical direction, and word lines are shown in the figures in a horizontal direction. However, in RRAM, bit lines and word lines each function the same. That is, what are typically referred to as bit lines and word lines are in fact interchangeable in RRAM. Functionally, bit lines and word lines may be referred to generally as access lines. A string of memory cells is defined herein to be a group of memory cells that are each connected to a common access line, e.g., a group of memory cells each connected to a local bit line, with each local bit line connected to a global bit line by a segmentation element, a group of memory cells each connected to a local word line, with each local word line connected to a global word line by a segmentation element, or a group of memory cells each connected to a global access line.
The select device of a variable resistance memory cell is typically a diode. Since there are numerous types of variable resistive elements, in some RRAM memories the select devices may be uni-directional diodes, and in other RRAM memories the select devices may be bi-directional diodes. When bi-directional diodes are used as select devices, they may be symmetrical or non-symmetrical, that is, forward and reverse turn-on voltages for a non-symmetric bi-directional diode may be different. The choice of the programmable element typically dictates the choice of the select device. For example, a phase change memory may have all of its current flow in one direction, and as such, use a uni-directional select device. Conductive bridge memory may use current flow in different directions for programming and erasing, and as such, use a bi-directional select device.
A portion of a memory array 300 according to an embodiment of the disclosure is shown in
A pair of biasing lines 314 and 316 are also connected to the local bit lines 308 and run, in one embodiment, parallel to word lines 310. Each of the biasing lines 314, 316 is connected to a local bit line 308 by a respective bias device 318, 320, which comprises a select device, like a memory cell, but unlike a memory cell, does not include a programmable element. Biasing line 314 is connected to a plurality of local bit lines 308 by a plurality of biasing devices 318, each biasing device 318 connected between the line 314 and a respective one of the local bit lines 308 in one direction, and biasing line 316 is connected to a plurality of local bit lines 308 by a plurality of biasing devices 320, each biasing device 320 connected between the line 316 and a respective one of the local bit lines 308, in the opposite direction. For example, if the biasing devices 318 and 320 are uni-directional diodes, current flow for biasing devices 318 flows from line 314 to the local bit lines 308, and current flow for biasing devices 320 flows from the local bit lines 308 to line 316. The biasing lines can be used to forward or reverse bias the local bit lines for selecting or unselecting specific local bit lines.
The biasing devices and segmentation elements do use area in an array. Compared to the size of segmentation transistors, however, the area used by the biasing devices and segmentation elements combined is much smaller for each global bit line than by transistors. Further, the biasing devices and segmentation elements will scale with the memory cells, whereas transistors do not scale with the memory cells.
The segmentation elements are in one embodiment the same elements as are used for the select devices for the variable resistance memory cells. Compared to segmentation transistors, the segmentation elements 304 are much smaller in size, are much easier to fabricate, and can scale with the cells themselves. That is, as cell size decreases, the segmentation element size will also decrease, saving both cost and die area. As word lines and bit lines are interchangeable in RRAM, the segmentation of the array may be performed on either or both of the sets of bit lines and word lines without departing from the scope of the disclosure.
While a single global bit line to local bit line segmentation is shown, it should be understood that additional segmentation may be used without departing from the scope of the disclosure. For example, segmenting from a global bit line to a regional bit line, and then to a local bit line, may be used. The same sub-segmenting may also be used for word lines.
Programming or erasing a variable resistance memory cell comprises applying a forward or reverse bias across it. The differences between read, program, and erase operations are determined by the cell itself, and voltage and/or current magnitude, duration, bias (reverse or forward), and timing and/or waveform. Some variable resistance memory cells use bi-directional current flow for operation, and some use uni-directional current flow. What distinguishes them is the waveform. For uni-directional cells, the select device is uni-directional, and for bi-directional cells, the select device is bi-directional.
Forward and reverse biasing cells for operation is shown in greater detail in
Appropriate voltages for forward and reverse biasing cells will vary depending upon, e.g., the turn-on voltage of the select devices, the leakage tolerance for the array, and the size and characteristics of the cells and the select devices. However, for forward biasing, voltages that are sufficient to turn on the select device for a selected cell, and to reduce leakage or turn off select devices for unselected cells and blocks are chosen. Diodes can leak current when a bias below a turn-on voltage is applied to them. The amount of leakage depends on the actual voltage applied, and voltages in one embodiment are chosen to keep unselected diodes off or to keep the leakage below an acceptable amount, the acceptable amount determined by the application of the array.
In
In the unselected block 504, word lines are left floating, and the forward bias voltage Vf is applied to the biasing lines. This places Vf minus a threshold voltage of biasing devices 318 on the local bit lines, and keeps segmentation elements 304 of the unselected block 504 off. For some modes of operation, it may be desired to lower the local bit lines of a block below a certain level. This may be accomplished in one embodiment by lowering the voltage bias applied to biasing line 316 below zero volts, for example to −2.5 volts. This will drag the local bit lines to a threshold voltage above −2.5. It can be seen that application of biasing voltages to the biasing lines allows for pulling up or dragging down the bias of the local bit lines to any desired level. A voltage versus current curve for
In
In unselected block 704, word line unselect voltage Vwlunsel is applied to all word lines and to the biasing lines 314 and 316, sufficient to keep segmentation elements 304 in unselected block 704 off. A voltage versus current curve for
A method 900 of operating a memory is shown in flow chart form in
The memory 1000 includes an array 1030 of memory devices such as the arrays of
Address buffer circuitry 1040 is provided to latch address signals provided through I/O circuitry 1060. Address signals are received and decoded by a row decoder 1044 and a column decoder 1046 to access the memory array 1030. It will be appreciated by those skilled in the art with the benefit of the present description that the number of address input connections depends on the density and architecture of the memory array 1030. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.
The memory 1000 reads data in the memory array 1030 by sensing voltage or current changes in the memory array columns using sense amplifier circuitry 1050. The sense amplifier circuitry 1050, in one embodiment, is coupled to read and latch a row of data from the memory array 1030. Data input and output buffer circuitry 1060 is included for bidirectional data communication as well as the address communication over a plurality of data connections 1062 with the controller 1010. Write circuitry 1055 is provided to write data to the memory array.
Memory control circuitry 1070 decodes signals provided on control connections 1072 from the processor 1010. These signals are used to control the operations on the memory array 1030, including data read, data write (program), and erase operations. The memory control circuitry 1070 may be a state machine, a sequencer, or some other type of controller to generate the memory control signals. In one embodiment, the memory control circuitry 1070 is configured to control the timing and generation of voltages for the methods for sensing, programming, and erasing of memory cells.
The memory device illustrated in
In summary, one or more embodiments provide a memory array with segmentation. The segmentation elements scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention.
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