A client playback architecture for a media content distribution system is provided. In the preferred embodiment, the client playback architecture is a Remote Direct Memory Access (RDMA) based architecture. The RDMA based architecture enables the client playback device to obtain media content from a central server in real-time or in substantially real-time as the media content is needed for playback at the client playback device. More specifically, the playback device includes RDMA enabled playback circuitry operating to perform RDMA transfers for select media content, buffer the media content received as a result of the RDMA transfers, and provide the media content for presentation to one or more associated viewers via one or more audio/video interfaces.
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16. A method comprising:
performing at least one direct memory access transfer via a network interface to transfer data stored in an address range for select media content from a storage unit of a media content server to a first buffer circuit; and
transferring the data from the first buffer circuit to a second buffer circuit based on a playback rate;
processing the data to provide the select media content in a format ready for playback; and
storing the data to enable playback of the select media content.
23. A computer program product stored on a non-transitory computer-readable storage medium and including instructions configured to cause a processor to carry out the steps of:
performing at least one direct memory access transfer via a network interface to transfer data stored in an address range for select media content from a storage unit of a media content server to a first buffer circuit;
transferring the data from the first buffer circuit to a second buffer circuit based on a playback rate;
processing the data to provide the select media content in a format ready for playback; and
storing the data to enable playback of the select media content.
1. A system comprising:
a network interface;
playback circuitry associated with the network interface comprising:
a first buffer circuit associated with the network interface and configured to:
receive an address range of select media content defining a range of addresses in a storage unit of a media content server in which the select media content is stored; and
perform at least one direct memory access transfer via the network interface to transfer data stored in the address range from the storage unit of the media content server to the first buffer circuit; and
a second buffer circuit associated with the first buffer circuit comprising:
a media content processing function configured to:
receive the data from the first buffer circuit based on a playback rate;
process the data to provide the select media content in a format ready for playback; and
store the select media content for playback.
24. A system comprising:
a media content server;
a network interface;
playback circuitry associated with the network interface comprising:
a first buffer circuit associated with the network interface and configured to:
receive an address range of select media content defining a range of addresses in a storage unit of the media content server in which the select media content is stored; and
perform at least one direct memory access transfer via the network interface to transfer data stored in the address range from the storage unit of the media content server to the first buffer circuit; and
a second buffer circuit associated with the first buffer circuit comprising:
a media content processing function configured to:
receive the data from the first buffer circuit based on a playback rate;
process the data to provide the select media content in a format ready for playback; and
store the select media content for playback.
2. The system of
a first buffer; and
a data mover function configured to receive the address range of the select media content and perform the at least one direct memory access transfer via the network interface to transfer the data stored in the address range from the storage unit of the media content server to the first buffer.
3. The system of
generate a first direct memory access transfer request based on an amount of storage available in the first buffer;
issue the first direct memory access transfer request to the network interface, wherein data received in response to the first direct memory access transfer request is stored in the first buffer.
4. The system of
a plurality of first buffer circuits comprising the first buffer circuit, wherein the first buffer circuit further comprises an address compare function configured to:
compare addresses of data received from the network interface in response to direct memory access transfer requests from the plurality of first buffer circuits to addresses requested by the first direct memory access transfer request to identify the data received in response to the first direct memory access transfer request; and
trigger storage of the data received in response to the first direct memory access transfer request in the first buffer.
5. The system of
6. The system of
7. The system of
generate a subsequent direct memory access transfer request to transfer a subsequent block of the address range when sufficient storage becomes available in the first buffer;
issue the subsequent direct memory access transfer request to the network interface, wherein data received in response to the subsequent direct memory access transfer request is stored in the first buffer.
8. The system of
9. The system of
a plurality of first buffer circuits including the first buffer circuit;
a plurality of second buffer circuits including the second buffer circuit; and
controllable switching circuitry configured to interconnect the plurality of first buffer circuits to the plurality of second buffer circuits in a desired manner.
10. The system of
receive user input identifying the select media content;
assign the select media content to the first buffer circuit of the plurality of first buffer circuits;
identify the second buffer circuit from the plurality of second buffer circuits to be used for playback of the select media content; and
control the controllable switching circuitry to interconnect the first buffer circuit to the second buffer circuit.
11. The system of
12. The system of
13. The system of
14. The system of
15. The system of
17. The method of
generating a first direct memory access transfer request based on an amount of storage available in a first buffer of the first buffer circuit;
issuing the first direct memory access transfer request via the network interface;
receiving data in response to the first direct memory access transfer request; and
storing the data received in response to the first direct memory access transfer request in the first buffer of the first buffer circuit.
18. The method of
receiving data in response to a plurality of direct memory access transfer requests comprising the first direct memory access transfer request issued by a plurality of first buffer circuits comprising the first buffer circuit;
comparing addresses of the data received in response to the plurality of direct memory access transfer requests to addresses of the first direct memory access transfer request to identify the data received in response to the first direct memory access transfer request; and
triggering storage of the data received in response to the first direct memory access transfer request in the first buffer of the first buffer circuit.
19. The method of
20. The method of
generating a subsequent direct memory access transfer request to transfer a subsequent block of the address range when sufficient storage becomes available in the first buffer of the first buffer circuit;
issuing the subsequent direct memory access transfer request via the network interface;
receiving the data in response to the subsequent direct memory access transfer request; and
storing the data received in response to the subsequent direct memory access transfer request in the first buffer of the first buffer circuit.
21. The method of
22. The method of
25. The system of
26. The system of
27. The system of
28. The system of
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This patent application claims priority to and is a continuation of co-pending U.S. patent application Ser. No. 13/178,954, entitled “RDMA BASED REAL-TIME VIDEO CLIENT PLAYBACK ARCHITECTURE,” filed on Jul. 8, 2011, which claims priority to and is a continuation of U.S. patent application Ser. No. 11/831,228, entitled “RDMA BASED REAL-TIME VIDEO CLIENT PLAYBACK ARCHITECTURE,” filed on Jul. 31, 2007, now U.S. Pat. No. 7,996,482, the disclosures of each of which are hereby incorporated herein by reference in their entireties.
The present invention relates to a media content distribution system and more particularly relates to an architecture for a client playback device in a media content distribution system.
Many new and novel systems are emerging for narrowcasting of advertisements in media distribution systems such as, for example, digital television distribution systems. As a result of narrowcasting advertisements, higher levels of advertisement-based revenue can be obtained. However as narrowcast becomes more targeted and the number of users in the system grows, current centralized media content distribution systems do not efficiently scale for cost, size, and power. Thus, new architectures are needed to allow real-time late-binding of advertisements while minimizing loading on these centralized media content distribution systems.
The present invention provides a client playback architecture for a media content distribution system. In the preferred embodiment, the client architecture is a Remote Direct Memory Access (RDMA) based architecture. The RDMA based architecture enables the client playback device to obtain media content from a central server in real-time or in substantially real-time as the media content is needed for playback at the client playback device. More specifically, the playback device includes RDMA enabled playback circuitry operating to perform RDMA transfers for select media content, buffer the media content received as a result of the RDMA transfers, and provide the media content for presentation to one or more associated viewers via one or more audio/video interfaces.
In one embodiment, the RDMA playback circuitry includes an array of RDMA enabled buffers, an array of playback buffers, and switching circuitry interconnecting the array of RDMA enabled buffers to the array of playback buffers. In operation, when playback of select media content is desired, RDMA is utilized to transfer the select media content to a corresponding RDMA enabled buffer. As the select media content is being transferred to the RDMA enabled buffer, the media content is transferred to a desired playback buffer via the switching circuitry according to a playback clock. The playback buffer stores and optionally processes the media content for presentation to one or more associated viewers via an associated interface.
Those skilled in the art will appreciate the scope of the present invention and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.
The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the invention, and together with the description serve to explain the principles of the invention.
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the invention and illustrate the best mode of practicing the invention. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
In general, the system 10 includes a centralized media content server 12 interconnected to a number of set-top box (STB) functions 14-1 through 14-N1 via a network 16, which in this example is a Local Area Network (LAN) 16. The LAN 16 may be any type of wired and/or wireless LAN. In one embodiment, the LAN 16 provides a 10 Gigabits per second (Gbps) or higher transfer rate using InfiniBand (IB) or some other RDMA enabled protocol. The centralized media content server 12 may additionally or alternatively be interconnected to a number of STB functions 18-1 through 18-N2 via a network 20, which in this example is a Wide Area Network (WAN) 20. The WAN 20 may be wired, wireless, or a combination thereof. In one embodiment, the WAN 20 is an optical network providing a 10 Gbps or higher transfer rate. RDMA over Transfer Control Protocol/Internet Protocol (TCP/IP), or iWARP, may be used in the protocol stack to provide reliable transport of RDMA traffic over the WAN 20. Note that, preferably, the centralized media content server 12 serves only the STB functions 14-1 through 14-N1 via the LAN 16 or the STB functions 18-1 through 18-N2 via the WAN 20. In the case of the STB functions 14-1 through 14-N1, the centralized media content server 12 is preferably a server located on the same premises as the STB functions 14-1 through 14-N1. For example, the centralized media content server 12 and the STB functions 14-1 through 14-N1 may be located in a particular user's home. In the case of the STB functions 18-1 through 18-N2, the centralized media content server 12 may be located at, for example, a headend of a video distribution network.
The STB functions 14-1 through 14-N1 and 18-1 through 18-N2 may alternatively be referred to herein as client devices. Each of the STB functions 14-1 through 14-N1 and 18-1 through 18-N2 may be, for example, a set-top box similar to those used in traditional digital television delivery systems, a component of a set-top box, a personal computer, a component of a personal computer, a portable media player similar to an iPod®, a mobile telephone, a Personal Digital Assistant (PDA), or the like. As discussed below, the STB functions 14-1 through 14-N1 and 18-1 through 18-N2 incorporate RDMA enabled playback functions which enable the STB functions 14-1 through 14-N1 and 18-1 through 18-N2 to utilize RDMA to obtain desired media content from the centralized media content server 12.
The centralized media content server 12 hosts media content 22. The media content may include, for example, video content such as movies, television programs, or video clips; audio content such as songs or radio programs; streaming video content such as broadcast television channels or IPTV channels; streaming audio content such as broadcast radio stations; advertisement content; or the like, or any combination thereof. The centralized media content server 12 also includes an RDMA enabled network interface 24. In the illustrated embodiment, the RDMA enabled network interface 24 includes a LAN optimized protocol stack 26 and/or a WAN optimized protocol stack 28. The LAN optimized protocol stack 26 may use the IB protocol or similar RDMA enabled protocol to carry RDMA traffic over the LAN 16. The WAN optimized protocol stack 28 may use RDMA over TCP/IP or similar RDMA enabled protocol to carry RDMA traffic over the WAN 20.
As discussed below in detail, under the control of the driver 32, the RDMA enabled playback circuitry 30 operates to effect RDMA transfers of select media content from the centralized media content server 12 (
The RDMA enabled playback circuitry 30 also operates to output the received video content using one or more audio/video (A/V) interfaces 46 for presentation to one or more associated users via a viewer interface 48. The A/V interfaces 46 may include, for example, a High Definition Multimedia Interface (HDMI) with or without High-bandwidth Digital Content Protection (HDCP) or similar Digital Rights Management (DRM) technology, a Digital Video Interface (DVI), a component video interface, an S-Video interface, a component A/V interface, or the like, or any combination thereof. The viewer interface 48 may be, for example, a television or other display, a sound system, or the like, or a combination thereof. While the viewer interface 48 is illustrated as part of the STB function 14-1, the present invention is not limited thereto. The viewer interface 48 may alternatively be a separate device.
In this example, the viewer interface 48 also includes one or more user input components such as, for example, input buttons or dials, a keypad, a wireless remote control, or the like. As such, the STB function 14-1 may also include a client control function 50 operating to receive inputs from the one or more associated users and to either: (1) pass the user inputs to the RDMA enabled playback circuitry 30, the driver 32, the A/V interface 46, a controller 52 of the STB function 14-1, or any combination thereof or (2) process the user inputs and control one or more of the RDMA enabled playback circuitry 30, the driver 32, the A/V interface 46, and the controller 52 based on the user inputs. For example, the client control function 50 may receive user inputs such as content selection inputs and playback control inputs such as pause, fast-forward, rewind, or the like. Upon receiving a content selection input, the client control function 50 may either provide the content selection input to the driver 32 or control the driver 32 to initiate playback of the selected media content. Similarly, upon receiving a playback control input, the client control function 50 may either provide the playback control input to the driver 32 and/or the RDMA enabled playback circuitry 30 or control the driver 32 and/or the RDMA enabled playback circuitry 30 according to the playback control input.
The controller 52 may be used to perform various functions. For example, in one embodiment, the centralized media content server 12 (
As one example of the use of the array of RDMA enabled FIFO buffer circuits 56-1 through 56-X, the STB function 14-1 may perform late-binding of targeted advertisements to select video content. More specifically, upon receiving a content selection from the user, the driver 32 may assign the RDMA enabled FIFO buffer 56-1 to obtain the selected video content and assign the RDMA enabled FIFO buffer 56-2 to obtain targeted advertisements to be inserted into the selected video content during playback. Assuming, for example, that the select video content is being presented to the viewer via the playback buffer circuit 58-1, the driver 32 controls the crossbar switch 60 such that the playback buffer circuit 58-1 is connected to the RDMA enabled FIFO buffer circuit 56-1 during playback of the select video content and is switched to the RDMA enabled FIFO buffer circuit 56-2 to present the targeted advertisements during advertisement (ad) slots. For more information regarding an exemplary late-binding method for a central or remote headend of a video distribution system that may be used to perform late-binding in the STB function 14-1, the interested reader is directed to U.S. patent application Ser. No. 11/685,479, entitled LATE-BINDING OF ADVERTISEMENTS USING RDMA CONNECTIVITY, filed on Mar. 13, 2007 and U.S. patent application Ser. No. 11/760,013, entitled MULTI-CLIENT STREAMER WITH LATE BINDING OF AD CONTENT, filed on Jun. 8, 2007, both of which are hereby incorporated herein by reference in their entireties.
As another example of the use of the array of RDMA enabled FIFO buffer circuits 56-1 through 56-X, the STB function 14-1 may utilize multiple RDMA enabled FIFO buffer circuits 56-1, 56-X to provide a Picture-In-Picture (PIP) feature or to otherwise present multiple media content items simultaneously.
In operation, when media content is selected for playback, the driver 32 identifies an RDMA address range for the selected media content at the centralized media content server 12 from, for example, the mapping published by the centralized media content server 12. The driver 32 then provides the RDMA address range to the RDMA data mover function 64 of the RDMA enabled FIFO buffer circuit 56-1, which has been allocated for the selected media content by, for example, the controller 52. Upon receiving the RDMA address range, the RDMA data mover function 64 generally operates to determine the available space in the FIFO buffer 62 and generates an RDMA transfer request for at least a segment of the RDMA address range based on the available space in the FIFO buffer 62. The RDMA data mover function 64 then provides the RDMA transfer request to the RDMA layer 44 (
Thereafter, as data is received from the RDMA layer 44, the RDMA address compare function 66 compares an address of the received data (“Received RDMA address”) to a next anticipated RDMA address to determine whether the received data is data received in response to the RDMA transfer request of the RDMA data mover function 64. This is important where more than one of the RDMA enabled FIFO buffer circuits 56-1 through 56-X have issued concurrent RDMA transfer requests. By comparing the RDMA address of the received data to the next anticipated RDMA address for the issued RDMA transfer request, the RDMA address compare function 66 ensures that only the requested data is clocked into the FIFO buffer 62. If the RDMA address of the received data is the next anticipated RDMA address, the RDMA address compare function 66 toggles a gated FIFO input clock provided to the FIFO buffer 62 to clock the received data into the FIFO buffer 62. The data may be clocked in as a bit, byte, word, or other format appropriate to the RDMA enabled network interface 34 and the FIFO buffer 62. The RDMA data mover function 64 then increments the next anticipated RDMA address, and the process continues until all of the requested data is stored in the FIFO buffer 62.
Note that, in an alternative embodiment, the data received from the RDMA layer 44 is a block of data from a block of RDMA addresses. Thus, additional circuitry may be used within or around the RDMA address compare function 66 to correctly clock the data into the FIFO buffer 62. Also, additional circuitry may be used to increment the next anticipated RDMA address value in response to receiving data for a block of RDMA addresses rather than receiving data for each RDMA address separately.
Once all of the data for the RDMA transfer request has been received, the RDMA data mover function 64 monitors the FIFO buffer 62 to determine when at least a threshold amount of space is available before issuing the next RDMA transfer request, if any, for the selected media content. The threshold amount may be, for example, when the status of the FIFO buffer 62 is equal to or less than almost full. If the threshold amount of space is available, the RDMA data mover function 64 generates an RDMA transfer request for a next segment of the address range for the selected media content item. From this point, the process continues until the data for the entire RDMA address range has been transferred to the FIFO buffer 62. Once the transfer is complete, the RDMA data mover function 64 provides a “transfer complete” signal to the driver 32. Note that the RDMA data mover function 64 may provide feedback to the driver 32 if the transfer failed, if a FIFO overflow condition exists, or if a FIFO underflow condition exists. If the transfer fails or if playback of the selected media content is terminated, the driver 32 may instruct the RDMA data mover function 64 to clear the current transfer and clear the FIFO buffer 62.
While the data corresponding to the selected media content item is being transferred to the FIFO buffer 62, the data is also being clocked out of the FIFO buffer 62 by a FIFO output clock. As discussed below, the FIFO output clock is a streaming video playback clock provided by the playback buffer circuit 58-1, 58-Y (
If the FIFO buffer 62 is not full, or alternatively after the FIFO buffer 62 has been reset, the RDMA data mover function 64 sets a starting address for an RDMA transfer request to the RDMA starting address of the RDMA address range for the select video content (step 106). The RDMA data mover function 64 then determines whether the FIFO buffer 62 is almost full (step 108). If the status of the FIFO buffer 62 is almost full, the RDMA data mover function 64 waits until a sufficient amount of data has been clocked out of the FIFO buffer 62 to reduce the status of the FIFO buffer 62 below almost full. The RDMA data mover function 64 then calculates an ending address for the RDMA transfer request based on an amount of space available in the FIFO buffer 62, as discussed below in detail (step 110). In the typical scenario, the FIFO buffer 62 is not large enough to store all of the select video content. As such, the RDMA data mover function 64 sets the ending address for the RDMA transfer request based on a determination of the amount of space available in the FIFO buffer 62 or, in other words, a determination of the largest data block size that can be guaranteed to fit into the FIFO buffer 62.
Once the starting address and ending address for the RDMA transfer request are set, the RDMA data mover function 64 initiates and completes an RDMA transfer using the RDMA transfer request (step 112). More specifically, the RDMA data mover function 64 initiates the RDMA transfer by providing the RDMA transfer request to the RDMA layer 44 of the RDMA enabled network interface 34 (
Once the RDMA transfer is complete, the RDMA data mover function 64 determines whether the ending address for the RDMA transfer request is equal to the RDMA ending address for the RDMA address range for the select video content (step 114). If so, the RDMA data mover function 64 notifies the driver 32 that the RDMA transfer is complete (step 116), and the process returns to step 100. If not, the RDMA data mover function 64 sets a starting address for a next RDMA transfer request to the ending address of the RDMA transfer request plus one (step 118), and the process returns to step 108. The process is repeated until the transfer of the entire RDMA address range for the select video content is complete or until the RDMA transfer is terminated as a result of, for example, the viewer selecting new video content for playback.
At this point, the RDMA data mover function 64 sets the ending address of the RDMA transfer request to a value equal to the starting address of the RDMA transfer request plus the range of the RDMA transfer request determined in steps 200-212 (step 214). The RDMA data mover function 64 then determines whether the ending address for the RDMA transfer request is greater than the RDMA ending address for the RDMA address range for the select video content (step 216). If not, the process proceeds to step 112 of
The RDMA data mover function 64 then monitors the gated FIFO input clock output by the RDMA address compare function 66 to determine whether the gated FIFO input clock has toggled (step 304). Note that the gated FIFO input clock is toggled by the RDMA address compare function 66 in response to receiving an RDMA address that is equal to the next anticipated RDMA address for the transfer in order to clock the corresponding data into the FIFO buffer 62. If the gated FIFO input clock has not toggled, the RDMA data mover function 64 determines whether a timeout period has expired for the RDMA transfer request (step 306). If so, the RDMA data mover function 64 notifies the driver 32 that the RDMA transfer request has failed (step 308). If the timeout period has not expired, the process returns to step 304.
Once the gated FIFO input clock has toggled to clock the data for the next anticipated RDMA address into the FIFO buffer 62, the RDMA data mover function 64 determines whether the next anticipated RDMA address, which is the RDMA address of the data just clocked into the FIFO buffer 62, is equal to the ending address of the RDMA transfer request (step 310). If so, the process proceeds to step 114 of
The client playback control function 72 may be implemented in software, hardware, or a combination thereof. For example, the client playback control function 72 may be implemented as a software application stored by the controller 52 (
The video buffer monitoring and transfer control function 74 generally operates to manage a streaming video clock 76 based on the status of the A/V playback buffer 70 and/or requests from the client playback control function 72. The streaming video clock 76 is provided to clock data out of the FIFO buffer 62 of the connected RDMA enabled FIFO buffer circuit 56-1, 56-X to the video processing function 68 via the crossbar switch 60 at a desired clock rate. The streaming video clock 76 may be enabled or disabled by the video buffer monitoring and transfer control function 74. For example, the streaming video clock 76 may be disabled when a user input has been received from the viewer requesting that playback be paused. More specifically, if the viewer sends a request to pause playback, the client playback control function 72 may relay the pause request to the video buffer monitoring and transfer control function 74. The video buffer monitoring and transfer control function 74 may then monitor the A/V playback buffer 70 to allow data to continue to be transferred to the A/V playback buffer 70 until, for example, the A/V playback buffer 70 is full. When the A/V playback buffer 70 is full, the video buffer monitoring and transfer control function 74 may disable the streaming video clock 76 to suspend the transfer of data from the RDMA enabled FIFO buffer circuit 56-1, 56-X until the A/V playback buffer 70 is no longer full as a result of, for example, the viewer resuming playback. Alternatively, the video buffer monitoring and transfer control function 74 may disable the streaming video clock 76 as soon as the pause request is received and subsequently re-enable the streaming video clock 76 when playback is resumed.
Note that upon enabling the streaming video clock 76, data begins to be clocked from the FIFO buffer 62 of the RDMA enabled FIFO buffer circuit 56-1, 56-X to which the playback buffer circuit 58-1 is connected via the crossbar switch 60. The data may be clocked from the FIFO buffer 62 as bits, bytes, words, or other appropriate format. Further note that additional circuitry may be used to perform serial to parallel data conversion, parallel to serial data conversion, or the like as needed or desired by the video processing function 68. As the data is clocked from the FIFO buffer 62, the video processing function 68 processes the data to provide the requested video content in a format ready for playback. The video content from the video processing function 68 is stored in the A/V playback buffer 70 for presentation to the one or more associated viewers via the A/V interface 46.
Returning to step 404, if the playback buffer does not need more data or if the data ready signal is not active, the video buffer monitoring and transfer control function 74 determines whether the A/V playback buffer 70 is nearly full (step 410). If not, the process returns to step 402. If so, the video buffer monitoring and transfer control function 74 determines whether the streaming video clock 76 is enabled (step 412). If not, the process returns to step 402. If so, the video buffer monitoring and transfer control function 74 disables the streaming video clock 76 (step 414), and the process returns to step 402.
The RDMA enabled playback circuitry 30 provides substantial opportunity for variation without departing from the spirit or scope of the present invention. For example, while the discussion above focuses primarily on video content, the present invention is not limited thereto. As another example, while the discussion above focuses on using the RDMA enabled playback circuitry 30 as part of a client architecture, the present invention is not limited thereto. More specifically, the RDMA enabled playback circuitry 30 may alternatively be implemented in a server or headend of a media content delivery system. In this alternative embodiment, each of the playback buffer circuits 58-1 through 58-Y may be allocated to a particular remote client device or a particular group of remote client devices. The RDMA enabled FIFO buffer circuits 56-1 through 56-X may be used to obtain media content for the playback buffer circuits 58-1 through 58-Y from a media content server via a LAN or WAN in a manner similar to that described above. The output of the playback buffer circuits 58-1 through 58-Y may then be delivered to the associated client devices via any type of delivery network such as, for example, an Internet Protocol (IP) based delivery network. Thus, as an example, the RDMA enabled playback circuitry 30 may be implemented as part of the multi-client streamer of U.S. patent application Ser. No. 11/760,013, entitled MULTI-CLIENT STREAMER WITH LATE BINDING OF AD CONTENT.
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present invention. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
Evans, Gregory M., Roberts, Thomas A., Evans, James
| Patent | Priority | Assignee | Title |
| 11489748, | Nov 24 2014 | ROKU, INC. | Generating playback configurations based on aggregated crowd-sourced statistics |
| Patent | Priority | Assignee | Title |
| 5155591, | Oct 23 1989 | GENERAL INSTRUMENT CORPORATION GIC-4 | Method and apparatus for providing demographically targeted television commercials |
| 5231494, | Oct 08 1991 | GENERAL INSTRUMENT CORPORATION GIC-4 | Selection of compressed television signals from single channel allocation based on viewer characteristics |
| 5959623, | Dec 08 1995 | Oracle America, Inc | System and method for displaying user selected set of advertisements |
| 5974398, | Apr 11 1997 | TWITTER, INC | Method and apparatus enabling valuation of user access of advertising carried by interactive information and entertainment services |
| 6128651, | Apr 14 1999 | KLAUSTECH LLC; KLAUSTECH, LLC | Internet advertising with controlled and timed display of ad content from centralized system controller |
| 6161127, | Jun 17 1999 | KLAUSTECH LLC; KLAUSTECH, LLC | Internet advertising with controlled and timed display of ad content from browser |
| 6574793, | Feb 25 2000 | Vulcan Patents LLC | System and method for displaying advertisements |
| 6584492, | Jan 20 2000 | KLAUSTECH LLC; KLAUSTECH, LLC | Internet banner advertising process and apparatus having scalability |
| 6697878, | Jul 01 1998 | Fujitsu Limited | Computer having a remote procedure call mechanism or an object request broker mechanism, and data transfer method for the same |
| 6698020, | Jun 15 1998 | Microsoft Technology Licensing, LLC | Techniques for intelligent video ad insertion |
| 6718551, | Jan 06 1997 | ALPHONSO INC | Method and system for providing targeted advertisements |
| 6738978, | Dec 09 1992 | Comcast IP Holdings I, LLC | Method and apparatus for targeted advertising |
| 6799326, | Jul 07 1998 | United Video Properties, Inc. | Interactive television program guide system with local advertisements |
| 6820277, | Apr 20 1999 | PRIME RESEARCH ALLIANCE E , INC , A CORPORATION OF BRITISH VIRGIN ISLANDS | Advertising management system for digital video streams |
| 6938268, | Jan 08 1998 | Video stream sharing | |
| 7039932, | Aug 31 2000 | PRIME RESEARCH ALLIANCE E , INC , A CORPORATION OF BRITISH VIRGIN ISLANDS | Queue-based head-end advertisement scheduling method and apparatus |
| 7076530, | Aug 31 2001 | INTERDIGITAL CE PATENT HOLDINGS | Multiple function modem including external memory adapter |
| 7100183, | Feb 02 2000 | COX COMMUNICATIONS, INC | System and method for transmitting and displaying targeted infromation |
| 7134132, | Feb 25 2000 | Vulcan Patents LLC | System and method for displaying advertisements |
| 7146627, | Jun 12 1998 | THOMSON LICENSING, S A S | Method and apparatus for delivery of targeted video programming |
| 7184433, | May 26 2000 | ARRIS ENTERPRISES LLC | System and method for providing media content to end-users |
| 7185353, | Aug 31 2000 | PRIME RESEARCH ALLIANCE E , INC , A CORPORATION OF BRITISH VIRGIN ISLANDS | System and method for delivering statistically scheduled advertisements |
| 7228555, | Aug 31 2000 | PRIME RESEARCH ALLIANCE E , INC , A CORPORATION OF BRITISH VIRGIN ISLANDS | System and method for delivering targeted advertisements using multiple presentation streams |
| 7245614, | Jun 27 2001 | Cisco Technology, Inc. | Managing access to internet protocol (IP) multicast traffic |
| 7281030, | Sep 17 1999 | Intel Corporation; Intel Corp | Method of reading a remote memory |
| 7328450, | Dec 19 1996 | Index Systems, Inc. | Method and system for displaying targeted advertisements in an electronic program guide |
| 7363643, | Aug 31 2000 | RPX Corporation | Real-time audience monitoring, content rating, and content enhancing |
| 7565450, | Apr 28 2000 | ONLINE VIDEO NETWORK, INC | System and method for using a mapping between client addresses and addresses of caches to support content delivery |
| 7571440, | Jul 23 1998 | Unisys Corporation | System and method for emulating network communications between partitions of a computer system |
| 7600037, | Oct 06 2000 | Apple Inc | Real time transmission of information content from a sender to a receiver over a network by sizing of a congestion window in a connectionless protocol |
| 7650617, | Jun 06 2001 | Sony Corporation | Advertisement insert apparatus and advertisement insert method, and storage medium |
| 7652594, | Apr 08 2005 | TRIGGER CALIFORNIA, INC | Architecture for creating, organizing, editing, management and delivery of locationally-specific information to a user in the field |
| 7716699, | Jun 29 2006 | Microsoft Technology Licensing, LLC | Control and playback of media over network link |
| 7743112, | Jan 11 2001 | MARLIN SOFTWARE, LLC | Secure electronic media distribution and presentation system |
| 7783773, | Jul 24 2006 | Microsoft Technology Licensing, LLC | Glitch-free media streaming |
| 7882531, | Feb 15 2007 | Sony Corporation | Multicasting system and multicasting method |
| 7996482, | Jul 31 2007 | ZAMA INNOVATIONS LLC | RDMA based real-time video client playback architecture |
| 20010034763, | |||
| 20020007413, | |||
| 20020019769, | |||
| 20020023165, | |||
| 20020078444, | |||
| 20020087402, | |||
| 20020087978, | |||
| 20020095454, | |||
| 20020124249, | |||
| 20020124251, | |||
| 20020138291, | |||
| 20020138440, | |||
| 20020138831, | |||
| 20020144263, | |||
| 20020161838, | |||
| 20020184403, | |||
| 20030004793, | |||
| 20030009432, | |||
| 20030028888, | |||
| 20030036974, | |||
| 20030061607, | |||
| 20030065804, | |||
| 20030149975, | |||
| 20030158957, | |||
| 20030165196, | |||
| 20040032881, | |||
| 20040049600, | |||
| 20040064574, | |||
| 20040111742, | |||
| 20040163101, | |||
| 20040225719, | |||
| 20040249969, | |||
| 20040261136, | |||
| 20040267880, | |||
| 20040267952, | |||
| 20050036555, | |||
| 20050039205, | |||
| 20050091160, | |||
| 20050097183, | |||
| 20050108776, | |||
| 20050160470, | |||
| 20050232304, | |||
| 20050251820, | |||
| 20050259947, | |||
| 20060036490, | |||
| 20060059042, | |||
| 20060059048, | |||
| 20060059242, | |||
| 20060075057, | |||
| 20060095507, | |||
| 20060107187, | |||
| 20060107302, | |||
| 20060110552, | |||
| 20060168616, | |||
| 20060212900, | |||
| 20060224761, | |||
| 20060230119, | |||
| 20060294555, | |||
| 20070011702, | |||
| 20070027755, | |||
| 20070028261, | |||
| 20070058670, | |||
| 20070065122, | |||
| 20070112971, | |||
| 20070136488, | |||
| 20070136522, | |||
| 20070136778, | |||
| 20070214480, | |||
| 20070265974, | |||
| 20080063005, | |||
| 20080127245, | |||
| 20080189412, | |||
| 20080240673, | |||
| 20080288556, | |||
| 20080301311, | |||
| 20090102969, | |||
| 20090178090, | |||
| 20130117621, | |||
| EP989722, | |||
| EP1067792, | |||
| EP1162840, | |||
| EP1418514, | |||
| EP1524602, | |||
| EP1528478, | |||
| WO14951, | |||
| WO147156, | |||
| WO171524, | |||
| WO219581, | |||
| WO245430, | |||
| WO254754, | |||
| WO3053056, | |||
| WO9905584, | |||
| WO9952285, |
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