An exemplary display device includes a transparent substrate and a semiconductor device bonded to the transparent substrate. The transparent substrate includes a first alignment mark. The semiconductor device includes a substrate and a second alignment mark positioned on the substrate. The second alignment mark includes a first pattern structure positioned on the substrate and a second pattern structure positioned on the first pattern structure. The first pattern structure includes a plurality of first non-transparent marks. The second pattern structure includes a second pattern surrounded by the first non-transparent marks. The second pattern is an alignable shape that corresponds to a shape of the first alignment mark on the transparent substrate.
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1. A semiconductor device, comprising:
a substrate; and
an alignment mark positioned on the substrate, the alignment mark comprising:
a first pattern structure stacked on the substrate and comprising a first pattern, the first pattern comprising a plurality of first marks that are non-transparent; and
a second pattern structure stacked on the first pattern structure and comprising a second pattern that is non-transparent and surrounded by the first marks in a plan view perspective; and wherein none of the plurality of first marks overlaps with the second pattern in the plan view perspective.
11. A display device, comprising:
a transparent substrate having a first alignment mark; and
a semiconductor device bond to the transparent substrate, the semiconductor device comprising:
a substrate; and
a second alignment mark positioned on the substrate, the second alignment mark comprising:
a first pattern structure stacked on the substrate and comprising a first pattern, the first pattern comprising a plurality of first marks that are non-transparent; and
a second pattern structure stacked on the first pattern structure and comprising a second pattern that is non-transparent and surrounded by the first marks in a plan view perspective;
wherein the second pattern is an alignable shape that corresponds to a shape of the first alignment mark on the transparent substrate; and none of the plurality of first marks overlaps with the second pattern in the plan view perspective.
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1. Technical Field
The present disclosure relates to a semiconductor device and a display device, and more particularly to an alignment mark of a semiconductor device connectable to a transparent substrate in a display device employing a Chip-on-Glass (COG) method.
2. Description of Related Art
In a display device employing a Chip-on-Glass (COG) method, which is a technique for directly mounting a driving IC (IC chip) on a transparent substrate without interposing an FPC (Flexible Printed Circuit) or similar designs, where electrode terminals provided on the transparent substrate are connected to the IC chip to drive the display device. The transparent substrate is provided with electrodes, such as pixel electrodes for driving the display device, and the electrode terminals for supplying signals from the IC chip to the electrodes. Pads of the IC chip are connected to the electrode terminals through protruding electrical contacts called solder balls hereinafter, and output the signals for driving the display device to the electrodes.
An alignment mark on the IC chip may be formed by etching one of layers of the IC chip to form a pattern. The pattern may consist of two contrasting shapes including a first shape that scatters incident light from the photodetector, and a second shape that efficiently reflects the incident light in an incident direction, such that the first shape appears dark and the second shape appears light. Accordingly, the second shape is used to align with the alignment mark on the transparent substrate.
However, because the first shape and the second shape are formed by the same layer, contrast between the bright region and the dark region of the alignment mark on the IC chip is apt to be low. Accordingly, it is difficult to detect the alignment mark on the IC chip with a photodetector or naked eyes, and therefore a highly accurate alignment may be difficult to obtain.
What is needed, therefore, is to provide an item which overcomes the above-mentioned problems.
Reference will be made to the drawing to describe specific exemplary embodiments of the present disclosure in detail.
The present disclosure relates to clearly visible alignment marks on a semiconductor device and a display device. When the semiconductor device is bonded to a transparent substrate of the display device (shown in
The liquid crystal panel 20 includes a first transparent substrate 101, a second transparent substrate 102, a common electrode 103, a plurality of pixel electrodes 104, a sealant 105, a liquid crystal layer 106, a first polarizer 107, a second polarizer 108, a plurality of metal wirings 109, and a plurality of electrode terminals 110. The first transparent substrate 101 and the second transparent substrate 102 face each other. The liquid crystal 106 is sandwiched between the first transparent substrate 101 and the second transparent substrate 102, and sealed in place using the sealant 105. The pixel electrodes 104 and the first polarizer 107 are positioned on two opposite sides of the first transparent substrate 101, and the pixel electrodes 104 are positioned on a side adjacent to the liquid crystal layer 106 of the first transparent substrate 101. The common electrode 103 and the second polarizer 108 are positioned on two opposite sides of the second transparent substrate 102, and the common electrode 103 is positioned on a side adjacent to the liquid crystal layer 106 of the second transparent substrate 102.
The metal wirings 109 and the electrode terminals 110 are positioned on the same side of the first transparent substrate 101 as the pixel electrodes 104. The electrode terminals 110 are connected to corresponding metal wirings 109. Driving signals such as data signals, common signals, or scanning signals are provided to the liquid crystal panel 10 via the metal wirings 109. The sealant 105 is doped with a plurality of conductive particles 111. The conductive particles 111 connect at least one metal wiring 109 to the common electrode 103 so that the common signals can be transmitted to the common electrode 103 via the corresponding metal wiring 109 and the conductive particles 111 in order.
The first transparent substrate 101 includes at least one alignment mark 112 positioned on the same side of the transparent substrate 101 as the electrode terminals 110. In the disclosure, the number of the at least one alignment mark 112 is two.
The IC chip 20 is mounted on the first transparent substrate 101 to connect with the metal wirings 110 via the solder balls 30. Referring to
The at least one alignment mark 202 is formed on the same surface of the semiconductor substrate 201 as the pads 204. In the disclosure, the number of the at least one alignment mark 202 is identical with the number of the at least one alignment mark 112. Accordingly, the number of the at least one alignment mark 202 is two. Correspondingly, two predetermined areas A at a peripheral of the IC chip 20 are designated to form the two alignment marks 202. However, the number of the at least one alignment mark 202 and the number of the at least one alignment mark 112 are not limited to two respectively, but may be, one, three, four, or more, for example. The semiconductor substrate 201 may be a silicon substrate, for example. The circuit area 203 is positioned between the two alignment marks 202. The circuit area 203 includes a plurality of circuit patterns composed of the circuit components (shown in
The two alignment marks 202 are detected along a Y direction by the photodetector 90, and then a position of the first transparent substrate 101 or the IC chip 20 is adjusted such that the two alignment marks 202 are aligned with the two alignment marks 112 respectively. When the two alignment marks 202 are aligned with the two alignment marks 112 respectively, the pads 204 on the IC chip 20 are bonded to the respectively corresponding electrode terminals 110 via the solder balls 30, such that the IC chip 20 is precisely mounted on the first transparent substrate 101. The driving signals from the IC chip 20 are supplied to the liquid crystal panel 10 via the pads 204, the solder balls 30, and the electrode terminals 110, in order to drive the liquid crystal panel 10 to display images.
Referring to
The first pattern structure 211 includes a first pattern 221, a first antireflection film 228, and a first interlayer insulation film 222. The first pattern 221 includes a plurality of first marks 221a and a plurality of first spaces 221b between the first marks 221a. The first pattern 221 is formed on the interlayer insulation layer 213. The first antireflection film 228 covers the first marks 221a of the first pattern 221. The first interlayer insulation film 222 covers the first pattern 221 and the first antireflection film 228, and fills the first spaces 221b. The first pattern 221 is formed by etching one of layers of the IC chip 20. The first marks 221a are non-transparent. The first antireflection film 228 may be made of titanium nitride (TiN), for example. In the embodiment, the first antireflection film 228 only covers the first marks 221a of the first pattern 221. The first pattern 221 is a dot pattern. In alternative embodiments, the first pattern 221 may be a grid pattern, or a spiral pattern, for example.
The second pattern structure 212 includes a second pattern 223 and a second interlayer insulation film 224. The second pattern 223 is formed on the first interlayer insulation film 222. The second interlayer insulation film 224 is formed on the second pattern 223 and the first interlayer insulation film 222. The second pattern 223 is a non-transparent cross-shaped pattern and formed by etching one of the layers of the IC chip 20. The first pattern 221 and the second pattern 223 are formed by etching different two layers of the IC chip 20. The second pattern 223 is not limited to the cross-shaped pattern, but may be any shape (alignable shape) that corresponds to a shape of the alignment mark 112 on the first transparent substrate 101. The second pattern 223 is surrounded by the first marks 221a, as viewed from the photodetector 90. Directly facing the second pattern 223, no first marks 221 are formed on the interlayer insulation layer 213.
A region where the second pattern 223 is positioned is defined as a first region A1, and other region of the predetermined area A except the first region A1 is defined as a second region A2. The first region A1 appears a bright area, and the second region A2 appears a dark area. Because the first pattern 221 and the second pattern 223 are positioned in two different layers of the IC chip 20, and a distance of the second pattern 223 to the semiconductor substrate 201 is greater than a distance of the first pattern 223 to the semiconductor substrate 201, the incident light reflected by the first marks 221a through the first antireflection film 228 to the photodetector 90 in an incident direction is absorbed and scattered by the second pattern structure 212. Correspondingly, the incident light emitted from the second region A2 to the photodetector 90 is reduced, compared with the incident light from the first region A1 to the photodetector 90. That is, a luminance difference between the first region A1 and the second region A1 is increased. Accordingly, a contrast ratio of the alignment mark 202 is improved. Therefore, position and shape of the alignment mark 202 is accurately detected when the IC chip 20 and the first transparent substrate 101 are aligned and bonded.
Referring to
Referring to
The transistor 225 includes a source doped area 231, a drain doped area 232, a polysilicon layer 233 positioned between the source doped area 231 and the drain doped area 232, a source electrode 234 positioned on the source doped area 231, a drain electrode 235 positioned on the drain doped area 232, a gate insulating layer 236 positioned on the polysilicon layer 233 and partially overlapped with the source doped area 231 and the drain doped area 232, a gate electrode 237 positioned on the gate insulating layer 236, an interlayer insulation layer 238 positioned on the gate electrode 237, the gate insulating layer 236, the source doped area 231, the drain doped area 232, the source electrode 234 and the drain electrode 235, and two transparent conductive layers 239. The interlayer insulation layer 238 has two contact holes (not labeled) respectively penetrating the interlayer insulation layer 238. One of the two transparent conductive layer 239 is connected to the source electrode 234 via one of the two contact holes, and the other one of the two transparent conductive layer 239 is connected to the drain electrode 235 via the other one of the two contact holes.
Differences between the transistor 236 and the transistor 235 include: first, ions doped in a source doped area 241 and a drain doped area 242 of the transistor 226 differ from irons in the source doped area 231 and the drain doped area 232 of the transistor 225; second, the transistor 226 further includes two lightly doped drain area 250, with one of the two lightly doped drain area 250 positioned between the source doped area 241 and a polysilicon layer 243, and the other one positioned between the drain doped area 242 and the polysilicon layer 243. One of the non-transparent metal wirings 227 connects the gate electrode 237 of the transistor 225 to a gate electrode 247 of the transistor 226. The source doped area 231, the drain doped area 232, the source doped area 241, the drain doped area 242, the lightly doped drain areas 250, the polysilicon layer 233, the polysilicon layer 243, the source electrode 234, the drain electrode 235, the gate electrode 237, and the gate electrode 247 are all non-transparent.
During a manufacturing process of forming the IC chip 20, the first pattern 221 and the second pattern 223 are formed by utilizing non-transparent objects positioned in different two layers of the circuit area 203, as long as the first pattern 221 are positioned between the second pattern 223 and the semiconductor substrate 201, so that the first pattern 221 can be formed simultaneously with the formation of one of the non-transparent objects in the circuit area 203, and the second pattern 223 can be formed simultaneously with the formation of another one of the non-transparent objects in the circuit area 203.
As the above described, the contrast ratio of the alignment mark 202 is improved. Therefore, the position and shape of the alignment mark 202 is accurately detected when the IC chip 20 and the first transparent substrate 101 are aligned and bonded.
Referring to
The third pattern structure 215 includes a third pattern 216, a second antireflection film 218, and a third interlayer insulation film 217. The third pattern 216 includes a plurality of second marks 216a and a plurality of second spaces 216b between the second marks 216a. The third pattern 216 is formed on the first interlayer insulation film 222. The second antireflection film 218 covers the second marks 216a of the third pattern 216. The third interlayer insulation film 217 covers the third pattern 216 and the second antireflection film 218, and fills the second spaces 216b. The first pattern 221, the second pattern 223, and the third pattern 216 are formed by etching different three layers of the of the IC chip 20. The second marks 216a are non-transparent. The second antireflection films 218 may be made of titanium nitride (TiN), for example. In the embodiment, the second antireflection film 218 only covers the second marks 216a of the third pattern 216. The third pattern 216 is a dot pattern. In alternative embodiments, the third pattern 216 may be a grid pattern, or a spiral pattern, for example.
Each of the first marks 221a partially overlaps with at least one second mark 216a. In the embodiment, a cross section of each of the first marks 221a and a cross section of each of the second marks 216a are both in a rectangular shape. An area of the cross section of each of second marks 216a is smaller than an area of the cross section of each of the first marks 221a. A corner of each of the first marks 221a partially overlaps with a corner of a separate second mark 216a. Because the second mark 216a further scatter the incident light from the photodetector 90, and a distance of the first pattern 221 to the second pattern structure 212 becomes greater, the contrast ratio of the first region A1 to the second region A2 is further increased.
The third pattern 216 can be formed simultaneously with the formation of one of the non-transparent objects in the circuit area 2, as long as the third pattern structure 215 is sandwiched between the first pattern structure 211 and the second pattern structure 212, or between the first pattern structure 211 and the semiconductor substrate 201.
Referring to
Referring to
Similarly to the first pattern structure 221, the third pattern structure 215 of the alignment mark 202 in the fourth embodiment not only includes a plurality of second marks 216a surrounding the second pattern 223, but also includes a plurality of second marks 216a directly facing the second pattern 223. In the embodiment, the second marks 216a are homogeneously (evenly) distributed in the third pattern structure 215. The second marks 216a partially overlap with the first marks 221a, respectively. In alternative embodiments, the second marks 216a do not overlap with the first marks 221a, respectively.
Although certain embodiments of the present disclosure have been specifically described, the present disclosure is not to be construed as being limited thereto. Various changes or modifications may be made to the present disclosure without departing from the scope and spirit of the present disclosure.
Yang, Chun-Ping, Zhang, Da-Pong
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Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jul 30 2013 | Fitipower Integrated Technology, Inc. | (assignment on the face of the patent) | / | |||
Jul 30 2013 | YANG, CHUN-PING | FITIPOWER INTEGRATED TECHNOLOGY, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 030909 | /0529 | |
Jul 30 2013 | ZHANG, DA-PONG | FITIPOWER INTEGRATED TECHNOLOGY, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 030909 | /0529 |
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