Exemplary methods of forming the semiconductor device, encompasses forming a first package with at least one first die on a packaging substrate that is removably coupled to a carrier. Forming a thermal contact pad on the first die package, with or without a surrounding seal ring, and bonding a second die package to the first die package where the thermal contact pad is between the two packages. Electrically coupling the first die package to the second die package with a set of conductive elements and removing the carrier from the first package.
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1. A method of forming a package-on-package semiconductor device, comprising:
electrically coupling at least two dies to a first die packaging substrate by a first set of conductive elements to form a first die package;
removably coupling the first die package to a carrier;
forming a thermal contact pad on the first die package;
bonding a second die package onto the first die package, wherein the thermal contact pad is between the first die package and the second die package;
electrically coupling the first die package to the second die package by a second set of conductive elements; and
removing the carrier from the first die package.
8. A method of forming a semiconductor device, comprising:
forming a top die package having a plurality of first dies on a top packaging substrate;
forming a bottom die package having at least one second die;
electrically connecting the top die package and the bottom die package with a first set of conductive elements;
providing a thermal contact pad between a top surface of the bottom die package and a bottom surface of the top packaging substrate, wherein the thermal contact pad thermally isolates the bottom die package from the top packaging substrate; and
surrounding the thermal contact pad, the top packaging substrate and the bottom die package with a molding compound.
15. A method of forming a semiconductor device comprising:
forming a top die package having at least two stacked dies on a top packaging substrate;
electrically coupling the at least two stacked dies to the top packaging substrate with a first set of conductive elements;
depositing a first molding compound on the top packaging substrate, wherein the first molding compound surrounds the at least two stacked dies and the first set of conductive elements;
forming a bottom die package having at least one die on a bottom substrate;
providing a thermal contact pad and a seal ring between a top surface of the bottom die package and a bottom surface of the top packaging substrate; and
electrically coupling the top die package to the bottom die package with a second set of conductive elements.
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electrically coupling the plurality of first dies to the top packaging substrate by a second set of conductive elements; and
electrically coupling the at least one second die to a bottom packaging substrate by a third set of conductive elements.
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The present application is a divisional of U.S. application Ser. No. 13/803,609, filed Mar. 14, 2013, which claims priority of U.S. Provisional Application No. 61,692,893, filed Aug. 24, 2012, the disclosures of which is incorporated herein by reference in their entireties.
A Package-on-package (PoP) semiconductor device is used for high density electronic devices, and typically includes a bottom package component and a top package component combined together to form the PoP semiconductor device. The bottom package component includes a bottom die attached to a bottom packaging substrate and the top package component includes a top die attached to a top packaging substrate. The bottom and top package components are coupled together by a set of conductive elements, e.g., solder balls. During operation of the PoP semiconductor device, the bottom die typically generates heat that can cause cracks within the conductive elements and damage to the top die which results in thermal stress and warpage of the PoP semiconductor device.
Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are examples, and are not intended to limit the scope of the disclosure.
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According to one or more embodiments, each die of the stacked dies 112 comprises a memory chip, a logic chip, or a processor chip. Further, although the plurality of stacked dies 12 only includes two dies, the present disclosure is not limited to the particular number of dies. The dies are not limited to being wire-bonded to the packaging substrate 111. Other methods for connecting the stacked die 112 to the packaging substrate 111 will be discussed below with reference to
The packaging substrate 111 is a laminated circuit board comprising alternating layers of non-conductive polymers, such as bismaleinide-triazine (BT), and patterned or non-patterned conductive layers. The packaging substrate 111 includes top contacts 114, conductive vias 117, and bottom contacts 118 for electrical connection to other components. Solder balls 119 are used to electrically or thermally connect the top package 110 to a second package (e.g., a bottom package 120). The solder balls 119 electrically conduct signals and power to the stacked die 112. In one or more embodiments, the solder balls 119 are replaced with other conductive elements, such as conductive bumps and conductive balls (as depicted in
Further, as shown in
The bottom package 120 is attached to the top package 110 and includes a die 122 on a lower substrate 123. The die 122 is electrically connected with the lower substrate 123 by conductive elements (e.g., 124 and 125). According to one or more embodiments, the lower substrate 123 is a single crystal silicon lower substrate having one or more conductive layers. In some embodiments, the substrate is a ceramic substrate or polymer substrate. In some embodiments, a lower substrate 123 is used during a wafer-level packaging (WLP) process to package many dies 122. In some embodiments, the entire packaging process, including attaching the bottom package 120 and the top package 110, is completed before the lower substrate 123 is diced. According to one or more embodiments, the substrate is used in various parts of the process as an interface between electrical connections. In some embodiments, the lower substrate is provided or formed over electrical contacts and includes dielectric material and conductive elements formed within the lower substrate and over the lower substrate.
According to one or more embodiments, the die 122 is a logic chip, a processor chip, a memory chip, or the like. In at least some embodiments, the conductive elements 124 are metal contacts and the conductive elements 125 are metal pillars formed of copper (Cu). Alternatively, according to other embodiments, the conductive elements 124 and 125 are solder bumps, solder balls, copper pillars, conductive bumps, solder caps, conductive balls, and under-bump metallurgies.
An electrical connection between the die 122 and other circuitry is provided by the conductive elements (e.g., solder balls 119) on one side of the lower substrate 123 and the conductive elements (e.g., solder balls 126) on the opposite side of the lower substrate 123.
During operation of the PoP structure 100, the top package 110 and the bottom package 120 generate heat. In some embodiments, the heat generated by the bottom package 120 is greater than that generated by the top package 110, and potentially causes damage to the top package 110. A seal ring 130 and a thermal contact pad 140 are provided between a top surface of the die 122 and a bottom surface of the packaging substrate 111 to minimize heat transfer from the bottom package 120 to the top package 110 and prevent thermal stress and warpage in the PoP structure 100. The seal ring 130 provides a seal to insulate the top package 110 from heat generated by the bottom package 120. The thermal contact pad 140 comprises at least one of an oxide material, a nitride material, a molding compound or a polymer material. According to one or more embodiments, the thermal contact pad 140 comprises an adhesive material, such as epoxy or tape. In other embodiments, the thermal contact pad 140 is another plastic or silicone material. According to various embodiments, suitable material for the thermal contact pad 140 has a thermal conductivity of about or less than 0.5 Watts/Celsius (W/° C.) and is suitable for semiconductor processing and use in a semiconductor device under various operating conditions.
A second molding compound 142 is molded on the lower substrate 123 and surrounds the bottom package 120 including the die 122, between the seal ring 130 and the thermal contact pad 140 (e.g., at an outside of the thermal contact pad 140 and interposed between portions (i.e. segments) of the thermal contact pad as shown in
According to one or more embodiments, the present disclosure is not limited to the use of solder balls 119 for electrically connecting the top package 110 with the bottom package 120.
The PoP semiconductor device 200 includes top package 110 as depicted in
Further, according to one or more embodiments, the present disclosure is not limited to the use of conductive vias 125 for electrically connecting the die 122 to the lower substrate 123.
The present disclosure is also not limited to the stacked die configuration in the top package 110 as shown in
The top package 410 and the bottom package 420 are electrically connected together by conductive elements (e.g., solder balls 425). The bottom package 420 includes a die 426 electrically connected with a second lower substrate 427 by conductive elements (e.g., vias 428 and contacts 429). A seal ring 430 is between the first upper substrate 415 and the die 426 of the bottom package 420. A thermal contact pad 440 is between the top package 410 and the bottom package 420. As shown, the thermal contact pad 440 is between a top surface of the die 426 and the first upper substrate 415 and adjacent to the seal ring 430. The thermal contact pad 440 is a non-continuous layer. A first molding compound 446 is one the first upper substrate 415 and surrounds the top package 410 including the first die 412 and the second die 413 and the conductive elements (e.g., metal vias 416 and metal contacts 417). A second molding compound 448 is provided on the second upper substrate 427. The second molding compound 448 surrounds the first molding compound 446. Further, the second molding compound 448 is between portions of the thermal contact pad 440 and the seal ring 430, and surrounds the conductive elements (e.g., solder balls 425, metal vias 428 and metal contacts 429).
Although the dies 412 and 413 are shown in a side-by-side configuration in
The present disclosure is not limited to a bottom package of a PoP semiconductor device having only a single die. According to one or more embodiments, the bottom package includes more than one die in a stacked wafer level package (WLP) structure having a thermal contact pad sandwiched between the dies to provide thermal isolation between the dies.
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The carrier 920 is then removed in
One or more embodiments include a method of forming a package-on-package semiconductor device encompassing a first package with at least one first die on a packaging substrate removably coupled to a carrier, forming a thermal contact pad on the first die package and bonding a second die package to the first die package where the thermal contact pad is between the two packages. The method further encompasses electrically coupling the first die package to the second die package with a set of conductive elements and removing the carrier from the first package.
One or more embodiments include a method of forming a semiconductor device by forming a top die package encompassing a plurality of first dies on a top packaging substrate and forming a bottom die package with at least one second die. A first set of conductive elements is used to electrically connect the top die package with the bottom die package; and a thermal contact pad is provided between the a top surface of the bottom die package and a bottom surface of the top packaging substrate. A molding compound is provided to surround the thermal contact pad, the top packaging substrate and the bottom die package.
One or more embodiments include a method of forming a semiconductor device, by forming a top die package encompassing at least two stacked dies on a top packing substrate, electrically coupling the at least two stacked dies to the top packaging substrate with a first set of conductive elements. Depositing a first molding compound on the top packaging substrate where the at least two stacked dies and the first set of conductive elements are surrounded by the first molding compound. Forming a bottom die package encompassing at least one die on a bottom substrate. Providing a thermal contact pad and a seal ring between a top surface of the bottom die package and a bottom surface of the top packaging substrate, and electrically coupling the top die package to the bottom die package with a second set of conductive elements.
Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations could be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
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Mar 11 2013 | YU, CHEN-HUA | Taiwan Semiconductor Manufacturing Company, Ltd | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 036340 | /0375 | |
Mar 11 2013 | YEH, DER-CHYANG | Taiwan Semiconductor Manufacturing Company, Ltd | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 036340 | /0375 | |
Aug 17 2015 | Taiwan Semiconductor Manufacturing Co., Ltd. | (assignment on the face of the patent) | / |
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