A method for fabricating a diode is disclosed. In one embodiment, the method includes forming a schottky contact on an epitaxial layer of silicon carbide (SiC) and annealing the schottky contact at a temperature in the range of 300° C. to 700° C. The schottky contact is formed of a layer of molybdenum.
|
1. A method for fabricating a diode, said method comprising:
forming a schottky contact on an epitaxial layer of silicon carbide (SiC) wherein a ring termination region is formed in said epitaxial layer of silicon carbide (SiC) below a passivation layer, and wherein said schottky contact comprises a layer of molybdenum (Mo);
annealing said schottky contact at a temperature in the range of 300° C. to 700° C.;
forming an ohmic contact that contacts said passivation layer and said schottky contact and overlies portions of said ring termination region;
forming a layer of amorphous silicon that has a top surface that fully lies underneath and contacts a bottom surface of said ohmic contact and a side surface of said passivation layer wherein at least a portion of said bottom surface of said ohmic contact lies above a structure other than said amorphous silicon; and
forming a polyimide layer over said layer of amorphous silicon and over said schottky contact wherein said layer of amorphous silicon contacts portions of said schottky contact.
17. A schottky diode comprising:
a substrate;
an epitaxial layer located adjacent to and above said substrate;
an edge termination implant formed in a termination region of said epitaxial layer below a passivation layer;
a schottky contact formed on said epitaxial layer, wherein said schottky contact comprises a layer of molybdenum;
an ohmic contact formed above said schottky contact that contacts said passivation layer and said schottky contact and overlies portions of said termination region;
a backside ohmic contact formed on a backside of said substrate;
forming a layer of amorphous silicon that has a top surface that fully lies underneath and contacts a bottom surface of said ohmic contact and a side surface of said passivation layer wherein at least a portion of said bottom surface of said ohmic contact lies above a structure other than said amorphous silicon; and
a polyimide layer formed to contact top and side surfaces of said ohmic contact and a surface of said layer of amorphous silicon and over said schottky contact wherein said layer of amorphous silicon contacts portions of said schottky contact.
9. A method for fabricating a diode, said method comprising:
forming a substrate;
forming an epitaxial layer of silicon carbide on said substrate;
forming an edge termination implant in an edge termination region of said epitaxial layer of silicon carbide (SiC) below a passivation layer;
forming a schottky contact on said epitaxial layer wherein said schottky contact comprises a layer of molybdenum (Mo);
annealing said schottky contact at a temperature in the range of 300° C. to 700° C.;
forming an ohmic contact layer above said schottky contact that contacts said passivation layer and said schottky contact and overlies portions of said edge termination implant;
forming a backside ohmic contact on a backside of said substrate;
forming a layer of amorphous silicon that has a top surface that fully lies underneath and contacts a bottom surface of said ohmic contact and a side surface of said passivation layer wherein at least a portion of said bottom surface of said ohmic contact lies above a structure other than said amorphous silicon; and
forming a polyimide layer to contact top and side surfaces of said ohmic contact and a surface of said layer of amorphous silicon and over said schottky contact wherein said layer of amorphous silicon contacts portions of said schottky contact.
2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
8. The method of
10. The method of
11. The method of
12. The method of
13. The method of
14. The method of
15. The method of
16. The method of
18. The diode of
19. The diode of
20. The diode of
21. The diode of
22. The diode of
23. The diode of
24. The diode of
|
This application claims priority to provisional application Ser. No. 60/820,807 filed on Jul. 31, 2006, which is hereby incorporated by reference to this specification.
This invention relates to a silicon carbide (SiC) Schottky diode with a molybdenum Schottky barrier contact.
A diode is an electronic component that restricts the direction of flow of electric current. More specifically, it allows electric current to flow in one direction, but blocks electric current flow in the opposite direction. Accordingly, a diode can be thought of as an electronic version of a mechanical check valve. Circuits that require current flow in only one direction typically include one or more diodes.
Schottky diodes are diodes that are formed from the contact between a metal and a semiconductor rather than from a p-n junction. They have a lower forward voltage drop than a standard p-n junction diode. Schottky diodes generally have much lower junction capacitance than p-n junction diodes. The lower junction capacitance contributes to their high switching speed and their suitability for high speed circuits and radio frequency (RF) devices such as mixers and detectors. In addition, Schottky diodes may be used in high voltage applications.
For use in high voltage applications, Schottky diode manufacturers seek to provide devices that have superior properties for reducing power loss. Parameters used by manufacturers to assess the performance of such diodes include forward current conduction and reverse voltage blocking characteristics. Devices that provide high forward current conduction and a high blocking voltage are ideal for high voltage, low loss applications. Challenges to the successful manufacture of such devices include intrinsic properties of the materials used to fabricate the devices and physical defects that may be present in those materials.
Silicon Carbide (SiC) has emerged as a promising material for high-voltage and low-loss power semiconductor devices because of its high critical electric field. Moreover, Schottky barrier diodes (SBDs) that use SiC are currently commercially available. However, these devices demonstrate poor performance in comparison with the ideal performance potential of SiC. More specifically, currently available SiC-SBDs do not fully realize the high performance (high-voltage, high current capacity, and low-loss) potential of SiC. In addition, currently available SiC-SBDs exhibit performance degrading defects in the SiC epilayer of high-voltage versions.
Accordingly, a need exists for a method of providing Schottky diodes with improved forward current conduction and reverse voltage blocking capacity. The present invention provides a method and that accomplishes this need.
A molybdenum Schottky contact is disclosed that provides an improvement, as compared to titanium and other potential Schottky contact materials, in forward current conduction and reverse voltage blocking performance. Additionally, the molybdenum Schottky contact provides greater device operating stability at high temperatures and allows a higher annealing temperature than does SiC Schottky diodes that use titanium (Ti) or nickel (Ni) Schottky contacts.
Additionally, a method for fabricating a diode is disclosed. The method includes forming a Schottky contact on an epitaxial layer of silicon carbide (SiC) and annealing the Schottky contact at a temperature in the range of 300 to 700° C. The Schottky contact is formed of a layer of molybdenum (Mo).
As a part of a disclosed method for fabricating a diode a substrate is formed, an epitaxial layer is formed on the substrate and an edge termination implant is formed in a termination region of the epitaxial layer. In addition, a Schottky contact is formed on the epitaxial layer and the Schottky contact is annealed at a temperature in excess of 600° C. Thereafter, an aluminum (Al) contact layer is formed above the Schottky contact. The Schottky contact is formed of a layer of molybdenum (Mo).
Also disclosed is a Schottky diode fabricated in accordance with processes described herein. In one embodiment the Schottky diode includes a substrate, an epitaxial layer located adjacent to and above the substrate, a field ring formed in a termination region of the epitaxial layer and a Schottky contact formed on the epitaxial layer. The Schottky contact is formed of a layer of molybdenum. An aluminum layer is formed above the Schottky contact.
In one embodiment, a high temperature (>600° C.) annealed Molybdenum (Mo) Schottky contact is disclosed that has superior properties (for instance, Schottky barrier height=1.2-1.3 eV and ideality factor<1.1) for reduction of power loss in a high-voltage SiC-SBD. The Schottky barrier height indicates the difference of potentials at an interface between a metal and a semiconductor. This parameter is important in the determination of device forward voltage and leakage current. The ideality factor provides a measure of the quality of the interface. In general, the ideality factor is from 1 to 2, this parameter being below 1.1 in a high quality interface such as the molybdenum Schottky contact disclosed herein.
In one embodiment, electronic power devices such as 4H—SiC junction-barrier Schottky diodes that include a Schottky contact as disclosed herein may be fabricated on 3 inch diameter 4H—SiC wafers. Schottky metal contacts may be obtained by sputtering or better by e-beam and thermal evaporation of Ti, Mo and Ni.
In one embodiment, the disclosed Schottky diode exhibits a blocking voltage of up to 1000V at room temperature and in the range of 77-400° K. In one embodiment, characteristics of the Schottky diode were evaluated with reference to current—voltage and capacitance—voltage measurements. The Schottky Barrier heights (SBH), the ideality factors, and the reverse leakage current on different designs, were measured and a morphological study related to the structure of failed devices was performed by high resolution scanning electron microscopy.
In one embodiment, Schottky barrier diodes with Mo as the Schottky barrier exhibit a blocking voltage similar to that obtained by standard Ti metallization but with a lower height barrier value. A consequence of the lower barrier value is a better performance in forward conduction as is shown in
These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures.
The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:
It should be noted that like reference numbers refer to like elements in the figures.
The present invention will now be described in detail with reference to a various embodiments thereof as illustrated in the accompanying drawings. In the following description, specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without using some of the implementation details set forth herein. It should also be understood that well known operations have not been described in detail in order to not unnecessarily obscure the present invention.
In the
Referring to
In operation, when a positive voltage is applied across the terminals represented by ohmic layer 15 and backside ohmic contact 16 forward current conduction is triggered as is shown at 17 in
Fabrication Process
Initially, in one embodiment, a prepared wafer that includes a SiC substrate (e.g., 10 in
Next, a photo resist strip may be performed using a 100:6 solution of H2SO4:H2O2 at 140° C. for 15 minutes. A second photo resist mask may then be applied followed by a buffer oxide etch (B.O.E.) of the structure using a 6:1 buffer chemical solution. The aforementioned operations serve to prepare the semiconductor structure for edge termination implants (e.g., 12 in
In one embodiment, the edge termination implants (e.g., 12 in
Subsequently, a photo resist strip may be performed using a 100:6 solution of H2SO4:H2O2 at a temperature of 140° C. for 15 minutes. Thereafter, another buffer oxide etch (B.O.E) using a 6:1 solution may be performed. The resulting structure may be precleaned using a 4:1.5:1.5 (volume) solution of H2SO4:H2O2:H2O at 90° C. for 10 minutes and a 4:1.5:1.5 (volume) solution of H2ODI.:HCL:H2O2 at 75° C. for 10 minutes. Next, the edge termination implants (e.g., 12 in
Subsequently, another preclean operation may be performed using a 4:1.5:1.5 (volume) solution of H2SO4:H2O2:H2O at 90° C. for 10 minutes and a 4:1.5:1.5 (volume) solution of H2ODI.:HCL:H2O2 at 75° C. for 10 minutes. In order to provide a polished surface, a low thermal oxide (LTO) TEOS deposition may be performed. Subsequently, sacrificial oxidation may be performed which may be followed by an oxide strip.
Thereafter, a preclean operation may be performed using a 4:1.5:1.5 (volume) solution of H2SO4:H2O2:H2O at 90° C. for 10 minutes and a 4:1.5:1.5 (volume) solution of H2ODI.:HCL:H2O2 at 75° C. for 10 minutes. Next, a low thermal oxide (LTO) TEOS deposition having a thickness of 1 micron may be performed (which provides passivation where TEOS is formed on the termination implant area). And, subsequently a TEOS oxidation may be performed. In one embodiment, the TEOS oxidation results in improved electrical properties as the oxide interface is maintained compact through these processes.
Next, operations that remove material and prepare the semiconductor structure (provide a contact opening) for metal deposition may be performed. The operations include the formation of a photo resist mask (third), the performance of a B.O.E. oxide etch (using a 6:1 buffer chemical solution), the performance of a photo resist strip (using a 100:6 solution of H2SO4:H2O2 at 140° C. for 15 minutes), the performance of a preclean operation (using a 4:1.5:1.5 volume solution of H2SO4:H2O2:H2O at 90° C. for 10 minutes and a 4:1.5:1.5 volume solution of H2ODI.:HCL:H2O2 at 75° C. for 10 minutes), and the performance of a B.O.E. clean. Back side ohmic contact may be formed on the cathode area using a selection of thin metal layer such us Ni or Ni—Al and subsequent temperature annealing in the range of 800-1000° C. to reduce the contact resistance
After the aforementioned operations have been performed a molybdenum Schottky barrier (e.g. Mo Schottky contact 14 in
Next a photoresist mask (fourth) may be applied. Thereafter, a metal etch may be performed (for device definition) and a photo resist strip executed. Subsequently, a contact metal preclean may be performed. These operations may be followed by amorphous silicon deposition (e.g., 1900 A) and a polyimide passivation (for stable electrical characteristics and increased blocking capability).
Thereafter, a fifth photoresist mask may be applied followed by an amorphous silicon etch and a high temperature polyimide cure. Finally, a contact metal preclean and backside reinforcement metallization operations may be performed (e.g., to form backside ohmic contact 16). In one embodiment, materials used to form backside ohmic contact 16 include but are not limited to titanium (Ti) (1000A), nickel (Ni) (4000A) and silver (Ag) (6000A). In other embodiments, other metal and thicknesses selection may be used.
Characteristics
A high temperature annealed Mo SiC-SBDs such as is shown in
The following Table A shows experimental results, employing Mo, Ti, and Ni Schottky contact layers at different temperatures.
TABLE A
Barrier
Barrier
Height
Height
Schottky
from
Ideality
from
Contact
IV (eV)
Factor
CV (ev)
ND (cm−3)
Ir @ 600 V
Mo
0.91
1.07
1.10
1.32E16
1000 μA
Mo
0.97
1.05
1.15
1.74E16
1000 μA
Mo
1.10
1.05
1.21
1.26E16
100 μA
Ti
0.85
1.04
0.91
1.12E16
100 μA
Ti
1.20
1.03
1.21
9.85E15
20 μA
Ni
1.45
1.10
1.65
9.91E15
100 μA
Ni
1.52
1.12
1.72
1.16E16
50 μA
In exemplary embodiments, a high temperature (>600° C.) annealed Molybdenum (Mo) Schottky contact is provided that has superior properties (Schottky barrier height=1.2-1.3 eV and ideality factor<1.1) for reduction of power loss in a high-voltage SiC-SBD. The Schottky barrier height indicates the difference of potentials at an interface between a metal and a semiconductor. This parameter is important in the determination of device forward voltage and leakage current. The ideality factor provides a measure of the quality of the interface. In general, the ideality factor is from 1 to 2, this parameter being below 1.1 in a high quality interface.
In one embodiment, electronic power devices such as 4H—SiC junction-barrier Schottky (JBS) diodes that include a Schottky barrier (SB) as disclosed herein may be fabricated on 3 inch diameter 4H—SiC wafers. Schottky metal contacts may be obtained by thermal and e-beam evaporation of Ti, Mo and Ni.
In one embodiment, the disclosed Schottky diode exhibits a blocking voltage of up to 1000V at room temperature and in the range of 77-400° K. In one embodiment, characteristics of the Schottky diode were evaluated with reference to current—voltage and capacitance—voltage measurements. The Schottky Barrier heights (SBH), the ideality factors, and the reverse leakage current on different designs, were measured and a morphological study related to the structure of failed devices was performed by high resolution scanning electron microscopy.
In one embodiment, Schottky barrier diodes with Mo as the Schottky barrier exhibit a blocking voltage similar to that obtained by standard Ti metallization but with a lower height barrier value. A consequence of the lower barrier value is a better performance in forward conduction as is shown in
Junction barrier Schottky (JBS) diodes limit the electric field strength on the Schottky barrier and thus also limit Schottky barrier lowering and reverse current flow.
At step 301, a substrate is formed. In one embodiment, the substrate is formed of SiC. At step 303, an epitaxial layer is formed on the substrate. In one embodiment, the epitaxial layer is formed of SiC (high quality).
At step 305, a termination implant is formed in a termination region of said epitaxial layer. In one embodiment, the field ring is formed by edge termination diffusion. Thereafter a back side ohmic contact may be formed on a cathode area using a selection of thin metal layer such us Ni or Ni—Al and subsequent temperature annealing in the range of 800-1000° C. to reduce the contact resistance.
At step 307, a Schottky contact is formed on the epitaxial layer. In one embodiment, the Schottky contact comprises a layer of molybdenum.
At step 309, a Schottky contact is annealed at a temperature in the range of 300 to 700° C. At step 311, an ohmic contact layer is formed above the Schottky contact. In one embodiment, the ohmic contact may include but is not limited to aluminum, copper or gold. At step 313 an ohmic contact is formed on the backside of the substrate.
With reference to exemplary embodiments thereof, a method for fabricating a diode is disclosed. In one embodiment, the method includes forming a Schottky contact on an epitaxial layer of silicon carbide (SiC) and annealing the Schottky contact at a temperature in the range of 300 to 700° C. The Schottky contact is formed of a layer of molybdenum.
Although many of the components and processes are described above in the singular for convenience, it will be appreciated by one of skill in the art that multiple components and repeated processes can also be used to practice the techniques of the present invention. Further, while the invention has been particularly shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that changes in the form and details of the disclosed embodiments may be made without departing from the spirit or scope of the invention. For example, embodiments of the present invention may be employed with a variety of components and should not be restricted to the ones mentioned above. It is therefore intended that the invention be interpreted to include all variations and equivalents that fall within the true spirit and scope of the present invention.
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
4036672, | May 14 1975 | Hitachi, Ltd. | Method of making a junction type field effect transistor |
4206540, | Jun 02 1978 | International Rectifier Corporation | Schottky device and method of manufacture using palladium and platinum intermetallic alloys and titanium barrier |
4618871, | May 25 1982 | Siemens Aktiengesellschaft | Schottky power diode |
4648175, | Jun 12 1985 | MagnaChip Semiconductor, Ltd | Use of selectively deposited tungsten for contact formation and shunting metallization |
4672738, | Sep 28 1984 | Siemens Aktiengesellschaft | Method for the manufacture of a pn junction with high breakdown voltage |
4796084, | May 13 1985 | Kabushiki Kaisha Toshiba | Semiconductor device having high resistance to electrostatic and electromagnetic induction using a complementary shield pattern |
4862244, | Mar 27 1984 | NEC Electronics Corporation | Semiconductor device having Schottky barrier between metal silicide and silicon |
4903189, | Apr 27 1988 | Fairchild Semiconductor Corporation | Low noise, high frequency synchronous rectifier |
4990994, | Sep 24 1985 | Sharp Kabushiki Kaisha | Electrode structure for silicon carbide semiconductors |
5003372, | Jun 16 1988 | MagnaChip Semiconductor, Ltd | High breakdown voltage semiconductor device |
5047833, | Oct 17 1990 | International Rectifier Corporation | Solderable front metal contact for MOS devices |
5113237, | Sep 20 1988 | Qimonda AG | Planar pn-junction of high electric strength |
5233215, | Jun 08 1992 | INTELLECTUAL VENTURES HOLDING 78 LLC | Silicon carbide power MOSFET with floating field ring and floating field plate |
5323040, | Sep 27 1993 | INTELLECTUAL VENTURES HOLDING 78 LLC | Silicon carbide field effect device |
5362975, | Sep 02 1992 | KOBE STEEL USA 79 W T ALEXANDER DR , 4401 BLDG | Diamond-based chemical sensors |
5384470, | Nov 02 1992 | KOBE STEEL U S A , INC | High temperature rectifying contact including polycrystalline diamond and method for making same |
5436174, | Jan 25 1993 | INTELLECTUAL VENTURES HOLDING 78 LLC | Method of forming trenches in monocrystalline silicon carbide |
5527745, | Mar 20 1991 | Crosspoint Solutions, Inc. | Method of fabricating antifuses in an integrated circuit device and resulting structure |
5689128, | Aug 21 1995 | Siliconix Incorporated | High density trenched DMOS transistor |
5712502, | Jul 27 1994 | Infineon Technologies AG | Semiconductor component having an edge termination means with high field blocking capability |
5747831, | Jul 01 1994 | Cree, Inc | SIC field-effect transistor array with ring type trenches and method of producing them |
5753938, | Aug 08 1996 | North Carolina State University | Static-induction transistors having heterojunction gates and methods of forming same |
5789311, | Sep 26 1994 | FUJI ELECTRIC CO , LTD | Manufacturing method of SiC Schottky diode |
5801836, | Jul 16 1996 | ABB Research LTD | Depletion region stopper for PN junction in silicon carbide |
5914500, | Jan 21 1997 | Cree, Inc | Junction termination for SiC Schottky diode |
5915179, | Jun 09 1995 | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | Semiconductor device and method of manufacturing the same |
5932894, | Jun 26 1997 | Cree, Inc | SiC semiconductor device comprising a pn junction |
5977605, | Aug 30 1995 | Cree, Inc | SiC Semiconductor device comprising a pn Junction with a voltage absorbing edge |
6040237, | Jul 16 1996 | Cree, Inc | Fabrication of a SiC semiconductor device comprising a pn junction with a voltage absorbing edge |
6040600, | Feb 10 1997 | Mitsubishi Denki Kabushiki Kaisha | Trenched high breakdown voltage semiconductor device |
6040617, | Dec 22 1992 | STMicroelectronics, Inc | Structure to provide junction breakdown stability for deep trench devices |
6100572, | Mar 20 1996 | International Rectifier Corp. | Amorphous silicon combined with resurf region for termination for MOSgated device |
6150246, | Mar 07 1996 | Microsemi Corporation | Method of making Os and W/WC/TiC ohmic and rectifying contacts on SiC |
6177712, | Dec 10 1996 | FUJI ELECTRIC CO , LTD | Schottky barrier diode having a guard ring structure |
6207591, | Nov 14 1997 | Kabushiki Kaisha Toshiba | Method and equipment for manufacturing semiconductor device |
6229194, | Jul 13 1998 | International Rectifier Corp. | Process for filling deep trenches with polysilicon and oxide |
6303986, | Jul 29 1998 | Silicon Light Machines Corporation | Method of and apparatus for sealing an hermetic lid to a semiconductor die |
6320205, | Jan 15 1999 | Infineon Technologies AG | Edge termination for a semiconductor component, a schottky diode having an edge termination, and a method for producing the schottky diode |
6330967, | Mar 13 1997 | Tessera, Inc | Process to produce a high temperature interconnection |
6353252, | Jul 29 1999 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device having trenched film connected to electrodes |
6362495, | Mar 05 1998 | Purdue Research Foundation | Dual-metal-trench silicon carbide Schottky pinch rectifier |
6373076, | Dec 07 1999 | Philips Electronics North America Corporation | Passivated silicon carbide devices with low leakage current and method of fabricating |
6410958, | Nov 27 2000 | Kabushiki Kaisha Toshiba | Power MOSFET having laterally three-layered structure formed among element isolation regions |
6432750, | Jun 13 2000 | Semiconductor Components Industries, LLC | Power module package having insulator type heat sink attached to rear surface of lead frame and manufacturing method thereof |
6441455, | Mar 06 1997 | International Rectifier Corporation | Low dosage field rings for high voltage semiconductor device |
6498368, | Dec 09 1999 | Hitachi, Ltd. | Power semiconductor device |
6509240, | May 15 2000 | Infineon Technologies Americas Corp | Angle implant process for cellular deep trench sidewall doping |
6514782, | Dec 22 1999 | Lumileds LLC | Method of making a III-nitride light-emitting device with increased light generating capability |
6562647, | Sep 13 1999 | Vishay Intertechnology, Inc. | Chip scale surface mount package for semiconductor device and process of fabricating the same |
6573534, | Sep 06 1995 | Denso Corporation | Silicon carbide semiconductor device |
6573537, | Dec 22 1999 | Lumileds LLC | Highly reflective ohmic contacts to III-nitride flip-chip LEDs |
6586801, | May 01 2000 | FUJI ELECTRIC CO , LTD | Semiconductor device having breakdown voltage limiter regions |
6605862, | Feb 22 2001 | NXP B V | Trench semiconductor devices |
6621122, | Jul 06 2001 | SILICONIX TECHNOLOGY C V | Termination structure for superjunction device |
6622380, | Feb 12 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods for manufacturing microelectronic devices and methods for mounting microelectronic packages to circuit boards |
6624522, | Apr 04 2000 | Infineon Technologies Americas Corp | Chip scale surface mounted device and process of manufacture |
6630698, | Sep 02 1998 | Infineon Technologies Austria AG | High-voltage semiconductor component |
6635944, | Dec 18 1998 | Infineon Technologies AG | Power semiconductor component having a PN junction with a low area edge termination |
6673662, | Nov 28 2000 | Cree, Inc. | Epitaxial edge termination for silicon carbide Schottky devices and methods of fabricating silicon carbide devices incorporating same |
6674126, | Feb 09 2001 | FUJI ELECTRIC CO , LTD | Semiconductor device |
6683347, | Jul 24 1998 | FUJI ELECTRIC CO , LTD | Semiconductor device with alternating conductivity type layer and method of manufacturing the same |
6700141, | Oct 20 2000 | FUJI ELECTRIC CO , LTD | Semiconductor device |
6713813, | Jan 30 2001 | Semiconductor Components Industries, LLC | Field effect transistor having a lateral depletion structure |
6740931, | Apr 17 2002 | Kabushiki Kaisha Toshiba | Semiconductor device |
6762455, | Sep 09 1999 | Infineon Technologies AG | Semiconductor component for high reverse voltages in conjunction with a low on resistance and method for fabricating a semiconductor component |
6764906, | Jul 03 2001 | Siliconix Incorporated | Method for making trench mosfet having implanted drain-drift region |
6768170, | Aug 09 2001 | SILICONIX TECHNOLOGY C V | Superjunction device with improved avalanche capability and breakdown voltage |
6791167, | Mar 28 2002 | Mitsubishi Denki Kabushiki Kaisha | Resin-molded device and manufacturing apparatus thereof |
6812282, | Sep 10 2002 | INEOS ABS JERSEY LIMITED | Thermoplastic compositions providing matt surface |
6828609, | Nov 09 2001 | Infineon Technologies Austria AG | High-voltage semiconductor component |
6844571, | Dec 22 1999 | Lumileds LLC | III-nitride light-emitting device with increased light generating capability |
6849900, | Apr 16 2003 | Kabushiki Kaisha Toshiba | Semiconductor device |
6897133, | Oct 31 2000 | STMICROELECTRONICS S A | Method for producing a schottky diode in silicon carbide |
6936850, | Sep 22 1999 | Infineon Technologies AG | Semiconductor device made from silicon carbide with a Schottky contact and an ohmic contact made from a nickel-aluminum material |
6949454, | Oct 08 2003 | Texas Instruments Incorporated | Guard ring structure for a Schottky diode |
6960829, | Mar 28 2002 | Polaris Innovations Limited | Method for producing a semiconductor wafer, semiconductor chip, and intermediate semiconductor product |
6979862, | Jan 23 2003 | Infineon Technologies Americas Corp | Trench MOSFET superjunction structure and method to manufacture |
6992340, | Jun 19 2002 | Kabushiki Kaisha Toshiba | Semiconductor device |
7034376, | Dec 25 2003 | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | Schottky barrier diode semiconductor device |
7073890, | Aug 28 2003 | Eastman Kodak Company | Thermally conductive thermal actuator and liquid drop emitter using same |
7166890, | Oct 21 2003 | SILICONIX TECHNOLOGY C V | Superjunction device with improved ruggedness |
7173284, | Aug 29 2001 | Denso Corporation | Silicon carbide semiconductor device and manufacturing method |
7262434, | Mar 28 2002 | Rohm Co., Ltd. | Semiconductor device with a silicon carbide substrate and ohmic metal layer |
7265045, | Oct 24 2002 | Qualcomm Incorporated | Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging |
7265388, | Aug 29 2003 | NATIONAL INSITUTE OF ADVANCED INDUSTRIAL SCIENCE & TECHNOLOGY | Semiconductor device |
7299538, | Jul 18 2002 | Wispry, Inc. | Method for fabricating micro-electro-mechanical systems |
7315081, | Oct 24 2003 | Infineon Technologies Americas Corp | Semiconductor device package utilizing proud interconnect material |
7394158, | Oct 21 2004 | SILICONIX TECHNOLOGY C V | Solderable top metal for SiC device |
7411218, | Mar 19 2004 | Semiconductor Components Industries, LLC | Method and device with durable contact on silicon carbide |
7492003, | Jan 24 2006 | SILICONIX TECHNOLOGY C V | Superjunction power semiconductor device |
7507650, | Mar 26 2004 | Central Research Institute of Electric Power Industry | Process for producing Schottky junction type semiconductor device |
7649213, | Sep 29 2004 | Kabushiki Kaisha Toshiba | Semiconductor device |
7687907, | Apr 16 2004 | Renesas Electronics Corporation | Semiconductor device and manufacturing method of the same |
7718470, | Oct 17 2007 | Phoenix Precision Technology Corporation | Package substrate and method for fabricating the same |
7777292, | Jun 30 2006 | Kabushiki Kaisha Toshiba | Semiconductor device |
7812441, | Oct 21 2004 | SILICONIX TECHNOLOGY C V | Schottky diode with improved surge capability |
7834376, | Mar 04 2005 | SILICONIX TECHNOLOGY C V | Power semiconductor switch |
8368165, | Oct 20 2005 | SILICONIX TECHNOLOGY C V | Silicon carbide Schottky diode |
8368211, | Mar 11 2004 | Infineon Technologies Americas Corp | Solderable top metalization and passivation for source mounted package |
8368223, | Oct 24 2003 | Infineon Technologies Americas Corp | Paste for forming an interconnect and interconnect formed from the paste |
20010043172, | |||
20010052601, | |||
20020063281, | |||
20020064930, | |||
20020076851, | |||
20020109211, | |||
20020171087, | |||
20020179909, | |||
20030006425, | |||
20030042538, | |||
20030075783, | |||
20030119300, | |||
20030127747, | |||
20030162355, | |||
20030168734, | |||
20030176031, | |||
20030183895, | |||
20040012930, | |||
20040051118, | |||
20040063240, | |||
20040070060, | |||
20040104489, | |||
20040110330, | |||
20040113264, | |||
20040135178, | |||
20040145380, | |||
20040150040, | |||
20040169262, | |||
20040207092, | |||
20040212011, | |||
20040212093, | |||
20040245570, | |||
20040262685, | |||
20050012143, | |||
20050023680, | |||
20050029557, | |||
20050034888, | |||
20050067630, | |||
20050072984, | |||
20050077615, | |||
20050082570, | |||
20050082611, | |||
20050091988, | |||
20050116344, | |||
20050136635, | |||
20050139947, | |||
20050200011, | |||
20050230715, | |||
20050253168, | |||
20060003514, | |||
20060065899, | |||
20060086939, | |||
20060145283, | |||
20060145319, | |||
20060214242, | |||
20060220027, | |||
20060226504, | |||
20060255423, | |||
20070222025, | |||
20070228505, | |||
20080237608, | |||
20080286968, | |||
20090067630, | |||
20090104738, | |||
20100068855, | |||
20110248284, | |||
20110278591, | |||
20140042459, | |||
DE10002362, | |||
DE19840032, | |||
EP604194, | |||
EP681326, | |||
EP958923, | |||
EP1349202, | |||
EP1739753, | |||
FR2579023, | |||
JP11087690, | |||
JP11087698, | |||
JP11348355, | |||
JP2000022178, | |||
JP2001313391, | |||
JP2002118268, | |||
JP2002158363, | |||
JP2002261295, | |||
JP2003074951, | |||
JP2003258271, | |||
JP2003273127, | |||
JP2004079988, | |||
JP2004099898, | |||
JP2004111759, | |||
JP2004221513, | |||
JP2005079339, | |||
JP2005286197, | |||
JP2005311347, | |||
JP2006100593, | |||
JP7302896, | |||
JP9036393, | |||
WO38242, | |||
WO143172, | |||
WO3038906, | |||
WO2005091988, | |||
WO2005093840, | |||
WO2006047382, | |||
WO2006074382, | |||
WO9727626, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jul 31 2007 | VISHAY-SILICONIX | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Date | Maintenance Schedule |
Nov 15 2019 | 4 years fee payment window open |
May 15 2020 | 6 months grace period start (w surcharge) |
Nov 15 2020 | patent expiry (for year 4) |
Nov 15 2022 | 2 years to revive unintentionally abandoned end. (for year 4) |
Nov 15 2023 | 8 years fee payment window open |
May 15 2024 | 6 months grace period start (w surcharge) |
Nov 15 2024 | patent expiry (for year 8) |
Nov 15 2026 | 2 years to revive unintentionally abandoned end. (for year 8) |
Nov 15 2027 | 12 years fee payment window open |
May 15 2028 | 6 months grace period start (w surcharge) |
Nov 15 2028 | patent expiry (for year 12) |
Nov 15 2030 | 2 years to revive unintentionally abandoned end. (for year 12) |