A technique for cancelling or reducing crosstalk signals between controlled oscillators in an integrated circuit is provided. The technique involves an arrangement adapted to reduce a crosstalk signal generated by a first controlled oscillator to a second oscillator both comprised in the integrated circuit, wherein both controlled oscillators are configured to output a respective clock signal. The arrangement comprises a detector adapted to detect the crosstalk signal generated by the first controlled oscillator to the second controlled oscillator, a crosstalk cancellation circuit adapted to generate a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal, and a cancellation signal injector adapted to introduce the cancellation signal into the second controlled oscillator.
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13. A method of reducing a crosstalk signal generated by a first controlled oscillator to a second controlled oscillator both comprised in an integrated circuit, each of the controlled oscillators adapted to output a respective clock signal, the method being performed by an electronic device and comprising the steps of:
the electronic device detecting a crosstalk signal generated by the first controlled oscillator (CO) to the second controlled oscillator (CO);
the electronic device generating a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal;
the electronic device injecting the cancellation signal into the second CO to reduce the crosstalk signal;
the electronic device detecting a second crosstalk signal generated by the second CO to the first CO;
the electronic device generating another cancellation signal having an amplitude substantially the same as that of the second crosstalk signal and a phase substantially opposite to that of the second crosstalk signal; and
the electronic device injecting the cancellation signal into the first CO to reduce the second crosstalk signal.
1. An arrangement for reducing crosstalk between a first controlled oscillator and a second controlled oscillator both comprised in an integrated circuit, each controlled oscillator (CO) adapted to output a respective clock signal, the arrangement comprising:
a first detector adapted to detect a crosstalk signal generated by the first controlled oscillator (CO) to the second controlled oscillator (CO);
a first crosstalk cancellation circuit adapted to generate a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal; and
a first cancellation signal injector adapted to introduce the cancellation signal into the second CO,
wherein the first detector comprises:
a mixer stage adapted to produce a mixed signal (m1(t)) by mixing the clock signal (S1(t)) generated by the second CO with a CO clock signal having a fixed relationship with the clock signal (S1(t)) generated by the second CO;
a filter adapted to at least partially remove at least one or more of one or more dc components and one or more undesired mixing products from the mixed signal (m1(t)) to produce a filtered signal;
a signal converter adapted to down-convert the filtered signal into a dc signal (m2(t)); and
an output for outputting the dc signal as an indication for the crosstalk signal.
11. A method of reducing a crosstalk signal generated by a first controlled oscillator to a second controlled oscillator both comprised in an integrated circuit, each of the controlled oscillators adapted to output a respective clock signal, the method being performed by an electronic device and comprising the steps of:
the electronic device detecting a crosstalk signal generated by the first controlled oscillator (CO) to the second controlled oscillator (CO);
the electronic device generating a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal;
the electronic device injecting the cancellation signal into the second CO to reduce the crosstalk signal,
the electronic device producing a mixed signal (m1(t)) by mixing the clock signal (S1(t)) generated by the second CO with a CO clock signal having a fixed relationship with the clock signal (S1(t)) generated by the second CO;
the electronic device at least partially removing at least one or more of one or more dc components and one or more undesired mixing products from the mixed signal (m1(t)) by filtering to produce a filtered signal;
the electronic device down-converting the filtered signal into a dc signal (m2(t)); and
the electronic device outputting the dc signal as an indication for the crosstalk signal.
10. A radio communication device, comprising:
an integrated circuit having a first controlled oscillator and a second controlled oscillator, each of the first controlled oscillator and the second controlled oscillator adapted to output a respective clock signal;
an arrangement for reducing a crosstalk signal generated by the first controlled oscillator to the second controlled oscillator, the arrangement comprising:
a first detector adapted to detect the crosstalk signal generated by the first controlled oscillator (CO) to the second controlled oscillator (CO);
a first crosstalk cancellation circuit adapted to generate a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal; and
a first cancellation signal injector adapted to introduce the cancellation signal into the second CO,
wherein the first detector comprises:
a mixer stage adapted to produce a mixed signal (m1(t)) by mixing the clock signal (S1(t)) generated by the second CO with a CO clock signal having a fixed relationship with the clock signal (S1(t)) generated by the second CO;
a filter adapted to at least partially remove at least one or more of one or more dc components and one or more undesired mixing products from the mixed signal (m1(t)) to produce a filtered signal;
a signal converter adapted to down-convert the filtered signal into a dc signal (m2(t)); and
an output for outputting the dc signal as an indication for the crosstalk signal.
2. The arrangement of
a controller adapted to provide a control signal to adjust at least one or more of the amplitude and the phase of the cancellation signal based on the indication for the crosstalk signal.
3. The arrangement of
a variable gain amplifier adapted to adjust the amplitude of the cancellation signal; and
a variable phase shift circuit adapted to adjust the phase of the cancellation signal.
4. The arrangement of
wherein the adjustment circuitry further comprises at least one of:
a first variable gain amplifier adapted to adjust an amplitude of the first cancellation signal component; and
a second variable gain amplifier adapted to adjust an amplitude of the second cancellation signal component, wherein the first crosstalk cancellation circuit is adapted to generate the cancellation signal as a sum of the first and second cancellation signal components with any amplitude adjustments.
5. The arrangement of
6. The arrangement of
7. The arrangement of
8. The arrangement of
9. The arrangement of
a second detector adapted to detect another crosstalk signal generated by the second CO to the first CO;
a second crosstalk cancellation circuit adapted to generate another cancellation signal having an amplitude substantially the same as that of the crosstalk signal detected by the second detector and a phase substantially opposite to that of the crosstalk signal detected by the second detector; and
a second cancellation signal injector adapted to introduce the other cancellation signal into the first CO.
12. The method of
the electronic device controlling at least one or more of the amplitude and the phase of the cancellation signal based on the indication for the crosstalk signal.
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This application is a 35 U.S.C. §371 National Phase Entry Application from PCT/EP2012/073331, filed Nov. 22, 2012, designating the United States, and also claims the benefit of European Application No. 11009463.8, filed Nov. 30, 2011 and U.S. Provisional Application No. 61/569,521, filed Dec. 12, 2011. The disclosures of all applications are incorporated herein in their entirety by reference.
The present disclosure relates to crosstalk reduction and particularly crosstalk reduction in an integrated circuit (IC) comprising multiple controlled oscillators (COs).
Clock signals are important to the functioning of radio communication systems. In such systems, clock signals are required for various purposes, such as synchronization. Without reliable, accurate clock signals, radio communication systems cannot work properly.
In many radio communication devices, such as mobile terminals, radio frequency (RF) clock signals are usually generated by certain on-chip components, e.g., by phase locked loops (PLLs) which can lock to an external crystal resonator as a reference clock input with various dividing factors. Normally, for different components of the device running at different frequencies, multiple PLLs are required in the integrated circuit. For example, for transmitter and receiver circuits of a mobile terminal running at different frequencies, at least two PLLs are usually required.
Multi-function mobile terminals have become popular in the recent years. As mobile terminals become more and more advanced and complicated, multiple RF clock signals are needed for different applications, such as Wireless LAN, Bluetooth, GPS, cellular communication, etc. Moreover, in some newly suggested radio standards, such as 3GPP TS 36.101 v.10.4.0 (2011-09), in order to increase communication data rate, carrier aggregation is suggested, where two or more RF clock signals may be required for the receiver and the transmitter, respectively.
However, creating RF clock signals using multiple PLLs is not an easy task, especially for on-chip integrated solutions. Among others, crosstalk between multiple PLLs is a serious problem.
More understanding of the crosstalk problem can be gathered from
Specifically, in
When multiple PLLs are integrated into a single chip, they will interfere with each other, and the crosstalk between their VCOs will become a critical issue which can degrade the performance of the PLLs. For example, the PLLs will suffer from increased phase noise, frequency shift, and difficulty in locking. In the worst case, the PLLs may fail to perform the locking. The crosstalk depends on several factors. Two typical factors are the physical distance and the frequency difference between two PLLs in question.
One way to reduce the crosstalk between multiple PLLs is to physically separate the PLLs apart. For instance, with reference to the LC-based PLLs illustrated in
A result from electromagnetic simulation for the coupling between the two inductors is shown in
Although this separation solution can reduce the crosstalk between multiple PLLs on a chip, it is sometimes impractical due to the requirement of a large silicon area. This is especially true where the chip for hosting the PLLs must be small. Thus, the solution could become expensive, in particular for implementations requiring deep nanometer CMOS techniques. Moreover, the metal usage for routing among the separation area between the two inductors could make the situation even worse.
It is therefore an object to cancel, minimize, or at least reduce the crosstalk between multiple COs arranged in an integrated circuit.
In a first aspect, an arrangement is provided for reducing a crosstalk signal generated by a first controlled oscillator (CO) to a second CO, both of which are comprised in an integrated circuit. Each CO is adapted to output a respective clock signal. The arrangement comprises a (first) detector adapted to detect the crosstalk signal and a (first) crosstalk cancellation circuit adapted to generate a cancellation signal. The cancellation signal is of substantially the same amplitude as that of the crosstalk signal, but the phase of the cancellation signal is substantially opposite to that of the crosstalk signal. Further, the arrangement comprises a (first) cancellation signal injector adapted to introduce the cancellation signal into the second CO.
The (first) detector may comprise a mixer stage adapted to produce a mixed signal by mixing the clock signal generated by the second CO with another CO clock signal, wherein the other clock signal has a (e.g., fixed) relationship with the clock signal generated by the second CO. The detector may further comprise a filter adapted to at least partially remove one or more direct current (DC) components and/or one or more undesired mixing products (such as integer times of the frequency difference between the second CO and another CO) from the mixed signal. The “filter” mentioned above may be implemented by one or more filter stages. As a result of the removal, a filtered signal is produced. The detector may further comprise a signal convertor adapted to convert, or down-convert, the filtered signal into a DC signal and an output for outputting the DC signal as an indication for the crosstalk signal.
The arrangement may further comprise a controller adapted to provide a controlled signal to adjust the amplitude and/or the phase of the cancellation signal. The adjustment may be performed based on the indication for the crosstalk signal.
The (first) crosstalk cancellation circuit of the arrangement may further comprise at least one of a variable gain amplifier and a variable phase shift circuit. The variable gain amplifier may be adapted to adjust the amplitude of the cancellation signal whereas the variable phase shift circuit may be adapted to adjust the phase of the cancellation signal.
The (first) crosstalk cancellation circuit may further comprise an adjustment circuitry adapted to adjust the cancellation signal, wherein the adjustment circuitry may comprise a quadrature phase splitter adapted to provide a first cancellation signal component with a first phase shift and to provide a second cancellation signal component with a second phase shift, where the difference between the first and second phase shifts is essentially 90 degrees. The adjustment circuitry may further comprise at least one of a first variable gain amplifier adapted to adjust an amplitude of the first cancellation signal component and a second variable gain amplifier adapted to adjust an amplitude of the second cancellation signal component, such that the (first) crosstalk cancellation circuit is adapted to generate the cancellation signal as a sum of the first and second cancellation signal components with any amplitude adjustment.
The signal converter mentioned above may comprise one of a rectifier and a component which comprises a low pass filter and an amplifier arranged such as to extract the magnitude of the filtered signal.
The (first) cancellation signal injector mentioned above may further comprise a buffer adapted to isolate the cancellation signal from the second CO. The (first) injector may further comprise a coupler for coupling the cancellation signal to the second CO. The coupler provides coupling of either an inductive type or a capacitive type. Furthermore, on-chip twisted differential transmission lines may be provided in the arrangement between the first CO and the second CO.
The above-mentioned arrangement may further comprise a second detector for detecting another crosstalk signal, this signal is being generated by the second CO to the first CO. The arrangement may further comprise a second crosstalk cancellation circuit adapted to generate another cancellation signal having an amplitude substantially the same as that of the crosstalk signal detected by the second detector and a phase substantially opposite to that of the crosstalk signal. Further, the arrangement may comprise a second cancellation signal injector adapted to introduce the other cancellation signal into the first CO.
According to a second aspect, this disclosure provides a radio communication device comprising one or more of the arrangements mentioned above. The radio communication device may be realized in the form of a mobile telephone, smartphone, data or network card, and so on.
According to a third aspect, a method is provided for reducing a crosstalk signal generated by a CO to a second CO, both comprised in an integrated circuit arrangement. Each CO may be configured to output a respective clock signal. The method comprises the steps of detecting a crosstalk signal generated by the first CO to the second CO, generating a cancellation signal having an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal, and injecting the cancellation signal into the second CO to reduce the crosstalk signal.
The step of detecting the crosstalk signal may further comprise producing a mixed signal by mixing the clock signal generated by the second CO with another CO clock signal having a fixed relationship with the clock signal generated by the second CO (“fixed” means that no other variable affects the relationship between the first and second clock signals). For example, the second clock signal may be derived from the first clock signal by letting the first clock signal pass, say, a phase shifter, a limiter, and/or a filter. (The “filter” may be implemented by one or more filters.) Thus, the second clock signal is more or less a copy of the first clock signal possibly with some modification but at least having the same dominant spectral components), at least partially removing one or more DC components and/or one or more undesired mixing products (such as integer times of the frequency difference between the first CO and the other CO) from the mixed signal by filtering to thereby produce a filtered signal, down-converting the filtered signal into a DC signal, and outputting the DC signal as an indication for the crosstalk signal.
Based on the indication for the crosstalk signal, the amplitude and/or the phase of the cancellation signal may further be controlled.
The method mentioned above may further comprise detecting a second crosstalk signal generated by the second CO to the first CO, generating another cancellation signal having an amplitude substantially the same as that of the second crosstalk signal and a phase substantially opposite to that of the second crosstalk signal, and injecting the cancellation signal into the first CO to reduce the second crosstalk signal.
In the following, the crosstalk reduction technique presented herein is further described with reference to the exemplary embodiments illustrated in the figures, in which:
In the following, for purposes of explanation and not limitation, specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent to those skilled in the art that this disclosure may be practiced in embodiments that depart from these specific details. For instance, although the exemplary embodiments are described in connection with reference to integrated circuits comprising two PLLs each having a controlled oscillator, such as a voltage controlled oscillator, which are for generating respective clock signals and comprise two inductors respectively which have a coupling coefficient K there between, it should be noted that the crosstalk reduction technique presented in this disclosure is not limited to the physical layout of any of the exemplary integrated circuits described below. For instance, more than two PLLs may be provided in the integrated circuit, other clock-generating components may replace the controlled oscillators, and so on.
Corresponding to the exemplary arrangement 10 shown in
The method comprises the following steps: At step 102, a crosstalk signal generated by the first controlled oscillator CO1 12 to the second controlled oscillator CO2 14 is detected. At step 104, a cancellation signal is generated which has an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite thereto. Then at step 106, the cancellation signal is injected into the second controlled oscillator CO2 14 to reduce the crosstalk signal.
In the following arrangements, which illustrate optional details of the second arrangement 10 illustrated in
The arrangement 30 further comprises a circuitry between the two controlled oscillators 32 and 34 for reducing the crosstalk there between. The circuitry is termed as an active leakage cancelation loop, ALCL. Arranged between the two controlled oscillators 32 and 34, the active leakage cancelation loop ALCL comprises a (first) detector CD1 40, adapted to detect the crosstalk signal (that is, the (first) detector CD1 40 may be regarded as a crosstalk detector). The active leakage cancelation loop ALCL further comprises a (first) crosstalk cancelation circuit ALC1 42, adapted to generate a cancelation signal, which has an amplitude substantially the same as that of the crosstalk signal and a phase substantially opposite to that of the crosstalk signal. Further, as figuratively indicated by the pointed arrow leaving the crosstalk cancelation circuit ALC1 42 to the second controlled oscillator VCO2 34 in the figure, the arrangement 30 further comprises a (first) cancelation signal injector 44 for introducing the cancelation signal into the second controlled oscillator VCO2 34.
Stable/periodical interference having fixed spectrum, introduced by supply networks, package or ESD protection circuits, can also be reduced by the cancelation signal. In presence of both electromagnetic coupling and stable/periodical interference, at the crosstalk frequency their effect can be merged together and viewed as one source of crosstalk signal.
In some implementations, the active leakage cancelation loop ALCL may further comprise a controller, as indicated by 46 in the arrangement 30 of
The arrangement 30 for crosstalk reduction shown in
On top of the single-loop implementation of
More specifically regarding the arrangement 50 shown in
In order to achieve crosstalk cancellation in both directions, two active leakage cancellation circuits ALC1 42 and ALC2 43 are provided in the ALCL, which create two respective cancellation signals each with substantially the same amplitude but a substantially opposite phase with respect to the respective crosstalk signals. Crosstalk detectors CD1 40 and CD2 41 are used to detect the crosstalk and create an error signal. A controller 46 may again be employed to generate a control signal for minimizing the crosstalk. The control signal may be in the form of a vector signal. That is, in the twin-loop implementation, each single loop comprises an active leakage cancellation circuit, a crosstalk detector, and preferably a controller. In many cases, two or multiple loops can share the same controller.
With respect to the twin-loop crosstalk cancellation arrangement, an example of which, 50, is shown in
It should be emphasized that the crosstalk reduction technique proposed in this disclosure not only can cancel the crosstalk between two controlled oscillators (of e.g., PLLs), but also can be, in general, applied to more general cases where crosstalk between more than two controlled oscillators needs reduction. However, for ease of understanding, the detailed description herein is mainly focused on the examples involving two controlled oscillators.
Referring to
An alternative to the exemplary active leakage cancellation circuit 60 of
With respect to the exemplary active leakage cancellation circuits 60 and 70 of
The coupler 68, 78 can be implemented in different ways. As two examples, couplers based on inductive coupling and capacitive coupling are illustrated in
A first exemplary crosstalk detector 80 is shown in
In an alternative case (also shown in
to a difference frequency Δfik=fLoi−fLok that is the difference frequency between the ith VCO and the kth VCO.
The self-mixing scheme can be expressed in the following formula:
After BPF filtering, the DC components and/or one or more undesired mixing products such as integer times of the frequency difference between COs, are removed, so basically only the term CiLk cos(α−β) is left at the output of the first mixer stage.
Reference is now made to
In the second mixer stage, the local clock signals are created by mixers mixLoik and mixLoqk where the clock signals from both VCOi and VCOk are mixed to create the difference frequency Δfik. After a low pass filter LPF which removes, among others, some higher order products, a clean difference frequency clock Lod(t) with spectrum shown in
If the difference frequency generation shown in
The requirement for the band pass filter is not stringent, as any two signals of undesired mixing products/inter-modulation products may create a crosstalk component by further mixing if the two signals have a frequency of Δfik. As the further mixing of the higher order inter-modulation products shown in
The amplifier Ampd may employ several stages, such as cascaded stages, to provide enough gain for the accurate detection about the crosstalk, and it is operating at the difference frequency, so AC coupling can be used for the connections between the stages, solving the difficult DC shift issues normally associated with a high gain amplifier.
The amplifier Ampb is operating at DC condition, the DC offset can be an issue. However, it can be solved by using chopping technique that modulates the flicker noise to higher frequency. One of the chopping switches can be placed at output of amplifier Ampb, and the other can be inserted at any node of the crosstalk detection path, such as m1(t), a1(t) and m2(t). The impact of the flicker noise in Ampb may also be reduced by increasing the gain in amplifier Ampd.
As the crosstalk signal is finally down-converted into a DC signal, only the amplitude of it is interesting. As an alternative, amplitude, envelope, power, or peak detection methods can be used in crosstalk detection. For example, a rectifier may be inserted before the LPFb, and the second mixer stage and the difference frequency clock generator may be removed, as shown in
In some applications, there may be two PLLs placed within a very small separation distance yet requiring a very low level of crosstalk between them (after reduction). As a consequence, the crosstalk detector may have a large dynamic range to cope with the initial level of detected crosstalk as well as the target level. In particular the amplifier Ampd should be kept out of saturation so as to ensure a correct error gradient to the controller. In this case, a variable gain amplifier may be required for Ampd so the gain setting is low at the of beginning of the calibration. As the calibration progresses the residual error becomes small, thus higher gain is required for the amplifier Ampd.
Because the residual signal is finally down-converted to a DC signal, the design of low pass filter LPF can be easy. For example, a first order RC filter may be sufficient to remove the difference frequency component and at least some of its undesired mixing products. However, the bandwidth of the LPF will impact the setup time due to the fact that the product fc·ts is a constant, where fc is the bandwidth and is is the setup time. For the first order LPF, the product is 0.35, reducing the bandwidth of the LPF may reduce the noise impact and increase the sensitivity of the detection.
However, on the other hand, it increases setup time for the residual signal and slows down the calibration speed. Therefore, a variable bandwidth may be preferable for the crosstalk detector. During the beginning of a calibration, a wider bandwidth of LPF may be employed, and the bandwidth will reduce as the calibration progresses. This also implies that the sampling frequency of the clock used in the ADC can be changed by the controller.
As the residual error signal is a DC signal, in a calibration procedure, the criteria of minimizing the error can be employed to reduce the crosstalk between the PLLs.
A further exemplary crosstalk detector is illustrated in
Another variation of
The controller can be implemented in many ways. One way is utilizing the general processor that already exists in a modern wireless communication device. Another way is to have a digital hardware comprising a finite state machine or logic and storage units performing a routine work of calibration.
For multiple PLL applications, the calibration can be done between all possible pairs. Assume there are m PLLs, then the calibrated pairs are:
Of course, for two PLLs having an enough separation distance or difference frequency, the calibration in this pair for reducing the crosstalk can be skipped, also depending on the radio standards.
After calibration, the residual error becomes small, and the normalized residual error can be approximated as
where ΔAik is the normalized residual amplitude error and Δθik is the residual phase error, respectively. It also gives the attenuation that one can expect by using this technique. To reach good calibration result, a good accuracy is required for both the active leakage cancellation circuit and the crosstalk detector.
On the other hand, linearity of both the phase and the amplitude in the active leakage cancellation circuit versus the control signal is not required, a monotone relation will suffice, and thus becomes feasible for implementation. For example, the active leakage cancellation circuit may be implemented using a combination of a coarse control and a fine control.
As for robustness, the leakage to be cancelled can be assumed to be very stable as it largely depends on the geometry of the physical circuit structure. Additionally, the propagation delays of the parasitic coupling and the active leakage cancellation have the same direction, resulting in a common mode effect. This helps to reach a good accuracy. 40-60 dB attenuation can be expected from this cancellation method.
The power consumption introduced by the active leakage cancellation is very small because the leakage power is low and because the control loop can operate intermittently.
The crosstalk reduction technique presented herein exhibits various advantages. Firstly, the technique accommodates more challenging transceiver requirements, such as the ones defined in certain radio communication standards suggesting flexible carrier aggregation support, which requires a plurality of PLLs or COs on a same chip (or die). Secondly, according to the technique, the accuracy of the cancellation is based on crosstalk detection. As the error signal may be converted into a DC signal, the accuracy of the cancellation can achieve a high level. Thirdly, as the crosstalk has limited power, the cancellation circuitry can be designed in a low power style, and it may not need to operate continuously. Further, the crosstalk cancellation technique presented herein can achieve significant chip area reduction compared to transceiver designs based on PLL separation (physical separation of PLLs) only. Moreover, the crosstalk cancellation technique presented herein allows for more flexible floor-planning in transceiver design. Last but not least, the crosstalk cancellation technique presented herein incurs virtually no Q reduction penalty.
Those skilled in the art will appreciate that the crosstalk reduction technique explained herein may be implemented using hardware circuitry, software, or a combination thereof. The software may be operable in conjunction with a programmed microprocessor or a general purpose computer, using an Application Specific Integrated Circuit (ASIC) and/or Digital Signal Processor (DSPs). It will also be apparent that when the crosstalk reduction technique is described as a method, it may also be embodied in a computer processor and a memory coupled to the processor, wherein the memory is encoded with one or more programs that perform the method when executed by the processor.
While the crosstalk reduction technique has been described with reference to the above embodiments, it is to be understood that the description is for illustration purposes only. Accordingly, it is intended that the invention be limited only by the scope of the claims appended hereto.
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