A driver circuit includes a high-side power transistor having a source-drain path coupled between a first node and a second node and a low-side power transistor having a source-drain path coupled between the second node and a third node. A high-side drive circuit, having an input configured to receive a drive signal, includes an output configured to drive a control terminal of said high-side power transistor. The high-side drive circuit is configured to operate as a capacitive driver. A low-side drive circuit, having an input configured to receive a complement drive signal, includes an output configured to drive a control terminal of said low-side power transistor. The low-side drive circuit is configured to operate as a level-shifting driver.
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13. A circuit, comprising:
a high-side power transistor having a source-drain path coupled between a first node and a second node;
a low-side power transistor having a source-drain path coupled between the second node and a third node;
a high-side drive circuit having an input configured to receive a drive signal and an output configured to drive a control terminal of said high-side power transistor, said high-side drive circuit including a capacitive driver; and
a low-side drive circuit having an input configured to receive a complement drive signal and an output configured to drive a control terminal of said low-side power transistor, said low-side drive circuit including a level-shifting driver;
wherein said capacitive driver comprises:
a first half-bridge driver having an input responsive to said drive signal;
a first bootstrap capacitor coupled between an output of the first half-bridge driver and the control terminal of the high-side power transistor;
an inverting circuit configured to invert the output of the first half-bridge driver;
a second bootstrap capacitor coupled between an output of the inverting circuit and a fourth node; and
a transistor having a source-drain path coupled between the control terminal of the high-side power transistor and the second node, said transistor having a control terminal coupled to said fourth node.
1. A circuit, comprising:
a high-side power transistor having a source-drain path coupled between a first node and a second node;
a low-side power transistor having a source-drain path coupled between the second node and a third node;
a high-side drive circuit having an input configured to receive a drive signal and an output configured to drive a control terminal of said high-side power transistor, said high-side drive circuit including a capacitive driver comprising a first bootstrap capacitor having a first capacitor terminal coupled to said input of the high-side drive circuit and a second capacitor terminal coupled to the control terminal of said high-side power transistor; and
a low-side drive circuit having an input configured to receive a complement drive signal and an output configured to drive a control terminal of said low-side power transistor, said low-side drive circuit including a level-shifting driver; and
wherein said capacitive driver comprises:
a first half-bridge driver having an input responsive to said drive signal; and
wherein the first capacitor terminal of the first bootstrap capacitor is coupled to an output of the first half-bridge driver;
an inverting circuit configured to invert the output of the first half-bridge driver;
a second bootstrap capacitor having a first capacitor terminal coupled to an output of the inverting circuit and a second capacitor terminal coupled to a fourth node; and
a transistor having a source-drain path coupled between the control terminal of the high-side power transistor and the second node, said transistor having a control terminal coupled to said fourth node.
2. The circuit of
3. The circuit of
a level shifting circuit having an input responsive to said complement drive signal; and
a second half-bridge driver having an input responsive an output of the level shifting circuit and an output coupled to the control terminal of said low-side power transistor.
4. The circuit of
5. The circuit of
a switching transistor having a source drain path coupled between the second capacitor terminal of the first bootstrap capacitor and the control terminal of the high-side power transistor, wherein a control terminal of the switching transistor is coupled to said first node.
6. The circuit of
7. The circuit of
8. The circuit of
9. The circuit of
10. The circuit of
11. The circuit of
14. The circuit of
15. The circuit of
a level shifting circuit having an input responsive to said complement drive signal; and
a second half-bridge driver having an input responsive an output of the level shifting circuit and an output coupled to the control terminal of said low-side power transistor.
16. The circuit of
17. The circuit of
a switching transistor having a source drain path coupled between the first bootstrap capacitor and the control terminal of the high-side power transistor, wherein a control terminal of the switching transistor is coupled to said first node.
18. The circuit of
19. The circuit of
20. The circuit of
21. The circuit of
22. The circuit of
23. The circuit of
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This application claims priority from Chinese Application for Patent No. 201410596357.0 filed Oct. 24, 2014, the disclosure of which is incorporated by reference.
This disclosure relates generally to buck-boost converter circuits, and more particularly to a drive circuit and method for driving an inverting buck-boost converter.
DC/DC converter circuits are widely used in battery-powered portable devices. Examples of such devices include: a smart phone, a smart watch, a camera, a media player and a number of other portable digital devices. In order to extend battery life, those skilled in the art recognize a need for high efficiency operation under a wide load range. In many instances, the total efficiency of the device is limited by the efficiency of the included inverting buck-boost converter. The reason for this is because greater switching losses arise in the inverting buck-boost converter and a more complex driving circuit design is needed for the inverting buck-boost converter. There is accordingly a need in the art to maximize the battery life by improving the efficiency of the inverting buck-boost converter.
To improve the efficiency of an inverting buck-boost converter, a driver architecture is disclosed which provides for improved light load efficiency. The architecture uses different drive techniques for the high-side and low-side power transistors. For example, the high-side driver utilizes a capacitive drive technique while the low-side driver utilizes a level shifting drive technique.
In an embodiment, a circuit comprises: a high-side power transistor having a source-drain path coupled between a first node and a second node; a low-side power transistor having a source-drain path coupled between the second node and a third node; a high-side drive circuit having an input configured to receive a drive signal and an output configured to drive a control terminal of said high-side power transistor, said high-side drive circuit including a capacitive driver; and a low-side drive circuit having an input configured to receive a complement drive signal and an output configured to drive a control terminal of said low-side power transistor, said low-side drive circuit including a level-shifting driver.
In an embodiment, a method comprises: receiving a drive signal; receiving a complement drive signal; driving a control terminal of a high-side power transistor having a source-drain path coupled between a first node and a second node in response to said drive signal using a capacitive driver circuit; and driving a control terminal of a low-side power transistor having a source-drain path coupled between the second node and a third node in response to said complement drive signal using a level-shifting driver circuit.
For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Reference is now made to
The control circuit 12 includes an oscillator circuit (OSC) 19 configured to generate a sawtooth oscillation signal and a pulse oscillation signal. The two signals have a same frequency. The pulse oscillation signal is applied to a control logic circuit 23 for use, for example, as a timing (clock) reference signal. A current to voltage conversion circuit (I to V) 21 converts a sensed current signal 20 to a voltage signal 22. The voltage signal 22 is then added (by summing circuit 24) to the sawtooth oscillation signal to generate a ramping signal 26. The ramping signal 26 is applied to a first input of a comparator (Comp) 33. A voltage divider circuit 28 receives a reference voltage VREF and generates a divided reference signal 30. The voltage divider circuit 28 is coupled between the reference voltage and an output node Vo2. The divided reference signal 30 is passed through a transconductance amplifier (Gm) 31 to generate a reference signal 32 that is applied to a second input of the comparator (Comp) 33. The comparator (Comp) 33 compares the ramping signal 26 to the reference signal 32 to generate a duty cycle control signal 34 that is applied to the control logic 23. The control logic 23 processes the duty cycle control signal 34 with reference to the pulse oscillation signal to output a first PWM control signal 36 (for high-side driving) and a second PWM control signal 38 (for low-side driving). These signals 36 and 38 may be referred to as DRV and DRV(bar).
The driver circuit 14 receives the first control signal 36 and the second control signal 38 and generates a high-side control signal 44 and a low-side control signal 46. In an example of an embodiment for the driver circuit 14, the first control signal 36 and the second control signal 38 are processed through a level-shifting circuit 40 and a drive amplifier 42 to generate the high-side control signal 44 and the low-side control signal 46, respectively. This implementation is shown in more detail with respect to
The power MOS circuit 16 includes a high-side drive transistor (MHS) and a low-side drive transistor (MLS) whose source-drain paths are connected in series at node LX2 between an input voltage node VIN and the output node Vo2. The transistors MHS and MLS are n-type power MOSFET devices. More particularly, in an embodiment, the transistors MHS and LHS are power NDMOS devices. The high-side transistor MHS is configured to be controlled by the high-side control signal 44, while the low-side transistor MLS is configured to be controlled by the low-side control signal 46. Current in the circuit path formed by the series connected source-drain paths of the transistors is sensed by a current sensing circuit 48. The output of the current sensing circuit comprises the signal 20 applied to the input of the I to V circuit 21.
The load circuit 18 includes a load inductance (represented by a resistive component Rind and inductive component L2) coupled between the node LX2 and a reference supply node such as ground (GND). The load circuit 18 further comprises a load capacitance (represented by a resistive component Rc and a capacitive component CL) coupled between the output node Vo2 and the ground reference supply node. The load circuit 18 further comprises a load resistance (represented by resistive component RL) coupled between the output node Vo2 and the ground reference supply node.
The power loss of the inverting buck-boost converter 10 can be divided into four parts corresponding to the control circuit 12, the driver circuit 14, the power MOS circuit 16 and the load circuit 18. So, there is a basic control block loss, a driver loss, a power MOS loss and a load (inductor) loss. Among these losses, the power MOS loss is composed of conduction loss and switching loss. The power loss can be expressed in accordance with the following equation:
Ploss=VIN×Iq+Ploss,driver+Ploss,switch+Ploss,rdson+Ploss,ind (1)
In Equation (1), it may be assumed that both VIN×Iq and Ploss,switch are constant because the driver speed and power MOS are the same. So, it is appropriate to just analyze the following losses:
Inductor loss:
Ploss,ind=Iind,rms2×Rind (2)
The drain-to-source resistance conduction loss (Rdson):
Ploss,rdson=Ihighside,rms2×Rdson,MHS+Ilowside,rms2Rdson,MLS (3)
The driver loss:
Ploss,driver=Ploss,driver,quie+Ploss,driver,switch (4)
In equations (2)-(4), Ploss,driver,quie is the driver quiescent loss, Ploss,driver,switch is the driver switching loss, Rdson,MHS is the high-side power MOS conduction resistance value, Rdson,MLS is the low-side power MOS conduction resistance value, and Rind is the inductor internal resistance. When considering portable device applications, a small packaged inductor is used and its internal resistance will be large. In such a case, the inductor loss makes a significant proportional contribution to total loss.
Reference is now made to
The circuit of
The regulating circuit for generating the voltage PCLAMP receives the voltage VIN and includes a current source 88, zener diode D1 and junction diode D2, transistor M5 and a resistor 90 connected in the manner illustrated. The regulating circuit for generating the voltage NCLAMP receives the voltage VIN and includes a current source 170, zener diode D3, transistor M6 and a resistor R3 connected in the manner illustrated. The drive signal DRV is applied to an inverter 160 and then applied to the level shift 2 circuit 162. The output from the level shift 2 circuit 162 is inverted by inverter 164 so as to ensure that the high and low-side circuits are not simultaneously actuated.
Assume that the converter circuit is operating in a steady state mode. The working waveform for a light load operation of the circuit of
Vgs,high=(VCLAMPD1−VGS5−0.7)×CBOOT/(CBOOT+Cgs,high).
At phase 2, t=DT, the DRV signal changes from logic 1 to logic 0. The high-side power MOS MHS switches off in response to transistor M2 and then the low-side power MOS switches on. The current in the inductor L2 starts to decrease. The voltage at node LX2 is pulled down to the voltage at node Vo2 by the low-side power transistor MLS. At this time, the capacitor CBOOT is again charged to VCLAMPD1−VGS5−0.7, and the energy saved in the inductor L2 is transferred to output node Vo2. If the loading is light enough, the control loop will enter DCM mode.
Turning next to phase 3, when current in the inductor drops to zero, both the high-side and low-side power transistors MHS and MLS are turned off until the next clock edge (oscillating pulse signal) is received (at time t=T). During this period of phase 3, the node LX2 is connected to the reference supply node ground through the ringkiller 82.
The calculation of loss at light load for the circuit of
Inductor loss:
Where:
So:
The drain-to-source resistance conduction loss (Rdson):
The driver loss:
It will be noted that the drive circuit of
Reference is now made to
The drive signal DRV is received and applied to an inverter 60 and thus complementary drive signals DRV and DRV(bar) are made available. Buffer amplifier circuits 62 and 64 receive the drive signals DRV and DRV(bar) and produce complementary buffered signals 66 and 68, respectively. The circuits 62 and 44 are powered from voltage supply node VIN. A high-side half bridge drive circuit formed by transistors M1 and M2 (also powered from supply node VIN) receives the signal 66 and outputs a first control signal at node A. A low-side half bridge drive circuit formed by transistors M3 and M4 receives the signal 68 and outputs a second control signal at node B. The coupled capacitor circuit is formed on the high and low-side by a pair of boost capacitors as described in detail below.
Turning first to the high-side circuit, the first control signal at node A is applied to an inverter circuit 70 and thus complementary first control signals are generated. The non-inverted first control signal (at node A) is applied to a bootstrap capacitor CBOOT1 coupled between node A and node VB1. The inverted first control signal (from inverter 70) is applied to a bootstrap capacitor CBOOT3 coupled between the output of the inverter 70 and node VB3. A junction diode D11 is coupled between node VB1 (at the cathode) and the input voltage node VIN (at the anode). A switch S1 is coupled between node VB1 and node C. The switch may be implemented as a MOS transistor (see,
With respect to the low-side circuit, the second control signal at node B is applied to an inverter circuit 72 and thus complementary second control signals are generated. The non-inverted second control signal (at node B) is applied to a bootstrap capacitor CBOOT2 coupled between node B and node VB2. The node VB2 is connected to the gate terminal of the low-side power MOS transistor MLS, with the current i2 applied through capacitor CBOOT2 to drive transistor operation. The inverted second control signal (from inverter 72) is applied to a bootstrap capacitor CBOOT4 coupled between the output of the inverter 72 and node VB4. A MOS transistor M6 has its source-drain path coupled between node VB2 and the output node Vo2. The gate terminal of transistor M6 is connected to node VB4. A zener diode D13 is coupled between node VB4 (cathode) and the node Vo2 (anode). A resistor R12 is coupled between node VB2 and node Vo2.
Assume that the converter circuit of
At phase 2, t=DT, the DRV signal changes from logic 1 to logic 0. The high-side driver transistor M1 switches from VIN to the reference supply voltage ground. The voltage at node VB1 is then coupled to VIN-VD. The switch S1 opens to disconnect the gate of transistor MHS from the capacitor CBOOT1. Current flows through diode D11 through capacitor CBOOT1 in the opposite direction to ground through transistor M2. The transistor M5 turns on and the high-side power transistor MHS is turned off. Then, the voltage at node VB2 is coupled to high and the low-side power transistor MLS turns on. Inductor current starts to decrease. If the load is light, this loop still works in PWM mode. When the current in the inductor drops to zero, the low-side power transistor MLS does not switch off until receipt of the next clock edge (oscillating pulse signal) at time t=T. The current in the inductor current is thus shown to reverse direction.
The calculation of loss for the circuit of
Inductor loss:
Where:
The drain-to-source resistance conduction loss (Rdson):
The driver loss:
Ploss,driver=Ploss,driver,switch (17)
The following Table compares the operation of the driving methodology of
FIG. 2 driver
FIG. 4 driver
Inductor
(Ahs + Als) × (I02)3/2 × Rind
(Bhs + Bls)I022 × Rind +
loss
(Chs + Cls) ×
Rind
DMOS
Ahs × (I02)3/2 × Ron,MHS + Als ×
(BhsI022 + Chs) × Ron,MHS +
conductor
(I02)3/2 × Ron,LHS
(BlsI022 + Cls) ×
loss
Ron,LHS
Driver
Ploss,driver,regulator +
loss
Ploss,driver,levelshift +
Ploss,driver,switch
Ploss,driver,switch
In a non-limiting example, consider VIN=3.7V, |Vo2|=4V, an inductor resistance of 0.25 ohm, a high-side drive transistor Rdson=0.2 ohm and a low-side Rdson=0.2 ohm. Then for the inductor and DMOS conductor loss:
FIG. 2 driver: Ploss,ind&rdson=0.6647×(I02)3/2 (18)
FIG. 4 driver: Ploss,ind&rdson=1.949I022+0.0028 (19)
Reference is now made to
The drive signal DRV is received and applied to an inverter 60 and thus complementary drive signals DRV and DRV(bar) are made available.
Turning first to the high-side drive circuitry: a buffer amplifier circuit 62 (powered from supply node VIN) receives the drive signal DRV(bar) and produces a buffered signal 66. A high-side half bridge drive circuit formed by transistors M1 and M2 (also powered from supply node VIN) receives the signal 66 and outputs a first control signal at node GPP. The coupled capacitor circuit is formed on the high-side by a pair of boost capacitors. The first control signal at node GPP is applied to an inverter circuit 70 and thus complementary first control signals are generated. The non-inverted first control signal (at node GPP) is applied to a bootstrap capacitor CB1 coupled between node GPP and node VB1. The inverted first control signal (from inverter 70) is applied to a bootstrap capacitor CB3 coupled between the output of the inverter 70 and node VB3. A diode-connected MOSFET M7 is coupled between node VB1 (at the cathode) and the input voltage node VIN (at the anode). A transistor M5(switch S1,
Turning next to the low-side drive circuitry: the drive signal DRV(bar) is received and applied to the input of a level shifter 162 powered from a regulated voltage NCLAMP. An inverter circuit 164 (also powered from the voltage NCLAMP) receives the level shifted drive signal DRV(bar) and produces a buffered signal 166. A half-bridge drive circuit formed transistors M3 and M4 (having series coupled source-drain paths coupled between NCLAMP and output node Vo2) is configured to receive the buffered signal 166 and generate a low-side drive signal at node GN. The node GN is connected to the gate terminal of the low-side power transistor MLS. The regulated voltage NCLAMP is generated by a circuit 168 including a current source 170 coupled in series with a zener diode D3 at node VCP1 between the input voltage node VIN and the output voltage node V02. A MOS transistor M6 is coupled to the input node VIN and configured to generate the voltage NCLAMP. A gate of the transistor M6 is coupled to node VCP1. A resistor R3 is coupled between the source of transistor M6, where the voltage NCLAMP is generated, and the output node Vo2.
The discontinuous mode detection (DMD) block 80 functions to detect the current across the transistor MLS when the low-side power MOS is on and high-side power MOS is off. When the sensed current decreases to zero, the DMD block 80 generates a signal (SDMD) that is applied to control logic (see,
Assume that the converter circuit of
At phase 2, t=DT, the DRV signal changes from logic 1 to logic 0. Here, the transistor M2 switches on. The voltage at node GPP is then pulled to low. The voltage at node VB1 is lower than the voltage VIN−VTH7 so current flows in the reverse direction through capacitor CB1 via diode-connected transistor M7 and transistor M2. The capacitor CB1 is then charged to the voltage VIN−VTH7 which causes the transistor M5 to be turned off, thus disconnecting the gate of transistor MHS from node VB1. At this time, the transistor M8 is turned on. The high-side power MOS MHS switches off by current drained through transistor M8. Then, the gate of the low-side power MOS transistor MLS is charged to high by a current flowing through transistors M6 and M3. The inductor current starts to decrease.
At phase 3, t=(D+D2)T, both high of the high and low-side power MOS transistors MHS and MLS are turned off. The node LX2 is shorted to GND through the discharged inductor L2.
The calculation of loss for the circuit of
Inductor loss:
The drain-to-source resistance conduction loss (Rdson):
Ploss,rdson=Ahs×(I02)3/2×Ron,MHS+Als×(I02)3/2×Ron,LHS (21)
The driver loss:
Ploss,driver=Ploss,lowside,driver,regulator+Ploss,lowside,driver,levelshift+Ploss,driver,switch (22)
Considering equation (22), it is noted that, in comparison to the
Reference is now made to
The driver of
It will be readily understood by those skilled in the art that materials and methods may be varied while remaining within the scope of the present disclosure. It is also appreciated that the present disclosure provides many applicable inventive concepts other than the specific contexts used to illustrate embodiments. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacturing, compositions of matter, means, methods, or steps.
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