A capacitive sensor that includes at least one capacitive element and a switched-capacitor readout circuit part for detecting at least one signal capacitance that results from motions of the capacitive element. The self-test bias voltage of the actuation circuit part is coupled to the capacitive element during a first period that is synchronized to the front end reset period and occurs when the self-test of the capacitive sensor is enabled by the self-test controller.
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18. A self-test method for a capacitive sensor that includes at least one capacitive element, a switched-capacitor readout circuit part for detecting at least one signal capacitance that results from motions of the at least one capacitive element, and a first switch arrangement configured to electrically couple the switched-capacitor readout circuit part to the at least one capacitive element for a front end readout period, and to electrically decouple the switched-capacitor readout circuit part from the at least one capacitive element for a front end reset period, the method comprising:
generating in the capacitive sensor a self-test bias voltage for electrostatic deflection of the at least one capacitive element during a first period, wherein the first period is synchronized to the front end reset period and is configured to occur when the self-test of the capacitive sensor is enabled;
electrically decoupling the self-test bias voltage from the at least one capacitive element in times other than the first period;
generating a self-test control signal, wherein a first state of the self-test control signal relates to the first period, and the second state of the self-test control signal relates to the times other than the first period; and
enabling and disabling generation of the self-test bias voltage by the high-voltage charge pump in response to the self-test control signal.
1. A capacitive sensor, comprising:
at least one capacitive element;
a switched-capacitor readout circuit configured to detect at least one signal capacitance that results from motions of the at least one capacitive element;
a first switch arrangement configured to electrically couple the switched-capacitor readout circuit part to the at least one capacitive element for a front end readout period, and to electrically decouple the switched-capacitor readout circuit part from the at least one capacitive element for a front end reset period;
a self-test controller configured to enable and disable a self-test of the capacitive sensor;
an actuation circuit configured to generate a self-test bias voltage for electrostatic deflection of the at least one capacitive element;
a second switch arrangement configured to electrically couple the self-test bias voltage of the actuation circuit part to the at least one capacitive element during a first period, wherein the first period is synchronized to the front end reset period and is configured to occur when the self-test of the capacitive sensor is enabled by the self-test controller, and to electrically decouple the actuation circuit part from the at least one capacitive element in times other than the first period,
wherein the actuation circuit includes a high-voltage charge pump and a high-voltage charge pump control circuitry configured to enable and disable generation of the self-test bias voltage by the high-voltage charge pump,
wherein the second switch arrangement is configured to generate a self-test control signal, a first state of the self-test control signal relating to the first period, and the second state of the self-test control signal relating to the times other than the first period, and
wherein the high-voltage charge pump control circuitry is responsive to the self-test control signal such that enabling and disabling generation of the self-test bias voltage by the high-voltage charge pump depends on the self-test control signal.
2. The capacitive sensor according to
a first clock pulse engine configured to run the front end readout period and the front end reset period in anti-phase and in a first frequency;
a second clock pulse engine configured to run the high-voltage charge pump in a second frequency; and
a high-voltage charge pump control circuitry responsive to the self-test control signal configured to enable the second clock pulse engine in the first period.
3. The capacitive sensor according to
4. The capacitive sensor according to
5. The capacitive sensor according to
6. The capacitive sensor according to
7. The capacitive sensor according to
at least one pair of capacitive elements, each including a variable capacitor, the capacitive elements forming a capacitive half bridge,
wherein the self-test bias voltage is coupled to induce opposite deflections of the capacitive elements.
8. The capacitive sensor according to
two or more capacitive elements;
element switches configured to control coupling of a common self-test bias voltage separately to the two or more capacitive elements,
wherein logic input changes of the element switches are configured to occur during the front end readout periods.
9. The capacitive sensor according to
one or more first control transistors configured to enable or disable coupling of the self-test bias voltage to the capacitive element according to a control signal; and
a high-voltage level shifter configured to use the time-discrete self-test bias voltage as a supply voltage to generate a shifted time-discrete voltage for use as the control signal of the first control transistors.
10. The capacitive sensor according to
one or more first control transistors configured to enable or disable coupling of the self-test bias voltage to the capacitive element according to a control signal; and
at least one floating charge pump coupled to the high-voltage charge pump output to generate a raised or lowered time-discrete voltage for use as the control signal of the one or more first control transistors.
11. The capacitive sensor according to
12. The capacitive sensor according to
13. The capacitive sensor according to
14. The capacitive sensor according to
the element switch is configured to input the self-test control signal, a first state of the self-test control signal relating to the first period, and the second state of the self-test control signal relating to the times other than the first period, and
wherein the medium-voltage supply to the second control transistors is enabled or disabled according to the state of the self-test control signal.
15. The capacitive sensor according to
the medium-voltage supply includes a medium-voltage charge pump,
the medium-voltage charge pump is coupled to a third clock pulse engine,
when self-test is disabled the third clock pulse engine is synchronized to the reset and readout periods so that output value of the medium-voltage charge pump becomes updated during front-end reset phases, and wherein
when self-test is enabled the third clock pulse engine applies a clock rate higher than the rate of change of the front end reset and readout periods.
16. The capacitive sensor according to
17. The capacitive sensor according to
19. The method according to
measuring the self-test bias voltage induced deflection of the at least one capacitive element during the front end readout period during the self-test;
comparing the measured deflection to a predefined deflection target value; and
determining the state of the at least one capacitive element based on the comparison.
20. The method according to
enabling the self-test bias voltage from the at least one capacitive element during the front end reset period of the self-test;
blocking the self-test bias voltage from the at least one capacitive element during the front end readout period;
measuring deflection of the at least one capacitive element during the front end readout period of the self-test;
comparing the measured deflection to a predefined return target value; and
determining the state of the at least one capacitive element based on the comparison.
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Field
The present invention relates to microelectromechanical devices and specifically to an inertial sensor with self-test capability and a self-test method for an inertial sensor.
Description of the Related Art
Capacitive microelectromechanical sensors have become part of many consumer devices and they are used also in a variety of safety critical applications. Especially in the latter case, it is important to identify potential failures in mechanical or electrical signal paths of the capacitive sensor.
In capacitive sensors, acceleration-like self-test signals can be generated using electrostatic forces. However, in order to mimic the full-scale acceleration induced motion of the micromechanical proof mass, voltages higher than nominal supply voltage are typically needed.
High voltages should preferably be generated locally because external high-voltage sources are often not available, especially in field conditions. On-chip generation of variable high-voltages is, however, often area consuming because high-ohmic resistive feedback is needed in order to scale down and control the magnitude of the generated high-voltage. Additionally, any discrete time circuitry or logic in high-voltage domain easily draws additional current. In some cases, high-voltage switches and logic increase complexity of the device because of limited gate-source voltage tolerance in switch transistors. Furthermore, use of resistors consumes not only circuit/chip area, but also power, because the pump needs to supply the current that flows through the resistive dividers. Large capacitors for enabling large current consumption from a charge pump circuitry consume significant circuit/chip area, and should be avoided.
An object of the present invention is to provide for a capacitive sensor local self-test capability that avoids or at least alleviates at least one of the above challenges. This objective of the present invention is achieved with a capacitive sensor and a self-test method described herein.
Embodiments of the present invention define a capacitive sensor that includes at least one capacitive element and a switched-capacitor readout circuit part for detecting at least one signal capacitance that results from motions of the capacitive element. A first switch arrangement is configured to electrically couple the switched-capacitor readout circuit part to the capacitive element for a front end readout period, and to electrically decouple the switched-capacitor readout circuit part from the capacitive element for a front end reset period. The capacitive sensor also includes a self-test controller configured to enable and disable a self-test of the capacitive sensor, and an actuation circuit part for generating a self-test bias voltage for electrostatic deflection of the capacitive element. A second switch arrangement is configured to electrically couple the self-test bias voltage of the actuation circuit part to the capacitive element during a first period. The first period is synchronized to the front end reset period and is configured to occur when the self-test of the capacitive sensor is enabled by the self-test controller, and to electrically decouple the actuation circuit part from the capacitive element in times other than the first period.
The actuation circuit part includes a high-voltage charge pump and a high-voltage charge pump control circuitry enabling and disabling generation of the self-test bias voltage by the high-voltage charge pump. The second switch arrangement is configured to generate a self-test control signal, a first state of the self-test control signal relating to the first period, and the second state of the self-test control signal relating to the times other than the first period. The high-voltage charge pump control circuitry is responsive to the self-test control signal such that enabling and disabling generation of the self-test bias voltage by the high-voltage charge pump depends on the self-test control signal.
Embodiments also define a self-test method for a capacitive sensor that includes at least one capacitive element, a switched-capacitor readout circuit part for detecting at least one signal capacitance that results from motions of the capacitive element, and a first switch arrangement configured to electrically couple the switched-capacitor readout circuit part to the capacitive element for a front end readout period, and to electrically decouple the switched-capacitor readout circuit part from the capacitive element for a front end reset period. The method comprises generating in the capacitive sensor a self-test bias voltage for electrostatic deflection of the capacitive element during first periods, wherein the first periods are synchronized to the front end reset periods and are configured to occur when the self-test of the capacitive sensor is enabled. The self-test bias voltage is decoupled from the capacitive element in times other than the first period.
The method further defines generating a self-test control signal, wherein a first state of the self-test control signal relates to the first period, and the second state of the self-test control signal relates to the times other than the first period; and enabling and disabling generation of the self-test bias voltage by the high-voltage charge pump in response to the self-test control signal.
Features and advantages of the claimed invention and its embodiments are described in more detail with the detailed description of the embodiments.
In the following the invention will be described in greater detail, in connection with preferred embodiments, with reference to the attached drawings, in which
The following embodiments are exemplary. Although the specification may refer to “an”, “one”, or “some” embodiment(s), this does not necessarily mean that each such reference is to the same embodiment(s), or that the feature only applies to a single embodiment. Single features of different embodiments may be combined to provide further embodiments.
In the following, features of the invention will be described with a simple example of a device architecture in which various embodiments of the invention may be implemented. Only elements relevant for illustrating the embodiments are described in detail. Various generic features of capacitive transducer structures or microelectromechanical devices that are generally known to a person skilled in the art may not be specifically described herein.
A single variable capacitor is created between a static electrode of the stator and a moving electrode of the proof mass. The total capacitance of the single variable capacitor includes a static capacitance defined by the capacitor configuration and a signal capacitance that results from the motion of the proof mass in response to external acceleration.
The capacitive sensor includes also a switched-capacitor readout circuit part 104 for detecting signal capacitances that result from motions of the capacitive elements 100, 102.
In Example 1 of
In capacitive detection, it is necessary to establish a zero point measurement, i.e. the switched capacitance circuit 104 needs to be reset between sampling periods. The capacitive sensor thus comprises a first switch arrangement S1 106 configured to electrically couple the readout circuit part 104 to the capacitive element for a front end readout period φread, and to electrically decouple the readout circuit part 104 from the one or more capacitive elements 100, 102 for resetting the readout circuit part 104 for a front end reset period φreset. This is illustrated in
In the present invention, this time-discrete nature of switched-capacitor detection is applied to implement an advanced high-voltage generating system to facilitate in-field self-test capability of the sensor device. For this, the capacitive sensor includes an actuation circuit part 108 for generating a bias voltage for electrostatic deflection of the one or more capacitive elements 100, 102. For self-test, the actuation circuit part 108 may be electrically coupled to the one or more capacitive elements 100, 102 during the front end reset periods φreset, and decoupled from them during the front end readout periods φread by means of a second switch arrangement S2 110. The second switch arrangement 110 is directly synchronized to the first switch arrangement S1 106.
The direct synchronization means that the second switch arrangement S2 110 is configured to electrically couple the actuation circuit part 108 to the capacitive element for a first period, wherein the first period is synchronized to the front end reset period and is configured to occur when the self-test of the capacitive sensor is enabled by the self-test controller. The second switch arrangement S2 110 is also configured to electrically decouple the actuation circuit part from the capacitive element in times other than the first period, i.e. when the self-test is not run and when the self-test is run, but a front end readout period is on. When the actuation circuit part is coupled to the capacitive element, the generated bias voltage creates an electrostatic force and causes a deflection to the capacitive element. The caused deflection may be detected during the readout period of the self-test and applied to determine whether the capacitive element operates normally or not.
The direct synchronization is illustrated with a block chart in
Returning to
Example 2 of
In order to create a necessary high-voltage for the self-test, the actuation circuit part 108 may include a charge pump. Charge pumps provide a way to increase voltages above the nominal supply of a circuit. The key component in charge-pump circuits is a non-linear charge transfer element that allows an alternating current input voltage to be rectified and increased.
The actuation circuit part 108 of
Right after start-up of the charge pump operation, the divided value of VHH remains below Vref, and the output of the comparator 502 is high. This allows a clock signal Clk of the charge pump clock input 508 to drive the charge pump through phases φ and
self-test
φread
φreset
ST(φreset)
1
1
0
1
1
0
1
0
0
1
0
1
0
0
1
1
Due to the inversion, when a self-test is not run, the self-test control signal ST(φreset) is ON, notwithstanding the state of the readout circuit part. When the self-test is run and the front end readout period φread is ON (i.e. the front end reset period φreset is OFF), the self-test control signal ST(φreset) is ON. When a self-test is run, and the front end readout period φread is OFF (i.e. the front end reset period φreset is ON), the self-test control signal ST(φreset) is OFF. When the self-test reset, control signal ST(φreset) is OFF, the charge pump is, in control of the charge pump control circuitry, enabled to generate a high-voltage input HV. It is understood that the logical operator and the inverted input scheme applied herein are exemplary only. Other mechanisms may be applied within the scope.
The actuation circuit part may also include switches s4 and s5 that are configured to reset the high-voltage net and the capacitive voltage division and the comparator during the front end readout period φread in order to implement direct current feedback for the charge-pump. When the capacitive voltage division is zeroed during reset, a desired voltage division ratio is maintained when the high-voltage output HV begins to rise.
In the exemplary structure of
Accordingly, during a front end reset period φreset, the high-voltage output HV may be used to create an electrostatic force that deflects the proof mass of the capacitive elements 100, 102 for self-testing of the capacitive sensor. In the example of
It is also possible to control the rise time of the high-voltage output. For example, precision of the high-voltage output signal can be increased by making the rise time deliberately slower for low high-voltage targets. This may be achieved by adding extra capacitive load to the high-voltage output node, which decreases the size of the high-voltage increment in a charge pump cycle. With the smaller step size, also the effects of comparator delay are reduced and the desired high-voltage level is achieved more accurately.
Advantageously, the clock rate of the pump (frequency of Clk) is significantly higher than the switching rate between the reset and readout periods (φreset, φreadout). Typically detection rates during self-tests are of the order of 10-100 kHz, while at least 10 MHz clock frequency for the charge-pump can be used. The capacitive sensor may thus include a first clock pulse engine configured to run the front end readout periods and the front end reset periods in anti-phase and in a first frequency, and a second clock pulse engine configured to run the switched capacitor charge pump in a second frequency. The ratio of the first frequency and the second frequency may then be advantageously of the order of 1:100 or more.
In another embodiment, illustrated in
The capacitive sensor includes at least one microelectromechanical element where one or more capacitive elements may be coupled together for joint detection in the electrical domain. The capacitive sensor may also include two or more microelectromechanical elements used, for example, for detection in different directions, or to provide two or more signals in one direction for improved robustness and/or accuracy. One important aspect of the self-test functionality is multiplexing, i.e. the ability to apply one and same high-voltage source for self-tests of more than one, preferably for self-tests of all capacitive elements in the capacitive sensor.
Returning to
In time-discrete multiplexed operation, an element HV switch may be configured to operate in three separate states. A first state relates to times when no high-voltage input is supplied, i.e. to periods when the self-test is not run, and to front end readout periods during the self-test. A second state relates to front end reset periods Φreset when a self-test is run, and high-voltage input HV needs to be fed to deflect the particular capacitive element of the element HV switch. A third state relates to front end reset periods Φread when a self-test is run, but the high-voltage input HV is to be fed to deflect another capacitive element in the capacitive sensor, not the one of the element HV switch.
These states may be managed in element HV switches with simple combinations of control signals.
The two logical states of the element-specific signal are represented in Figure with signals en_hvN (capacitive element N to be deflected) and dis_hvN (capacitive element other than N to be deflected). In the configuration of
State
dis_hvN
en_hvN
ST(Φreset)
HV
Vctrl_p
mems_eN
1
1
0
1
vss
vddint
highZ
2
0
1
0
HV
vss
HV
3
1
0
0
HV
HV
vss
When a self-test is run, during the front end reset period φreset of the capacitive sensor, the non-zero high-voltage input HV to the capacitive element is controlled by a respective element HV switch. As shown in
It is possible to bias the pass-transistors mp0 and mp1 to an internal supply voltage vddint, and thereby secure that they remain in a non-conductive state during front end readout periods (the first state). The vddint biasing may be controlled by a transistor mn2. In order to appropriately operate the transistor mn2, a medium-voltage charge pump 802 may be used to provide a voltage higher than vddint. The element HV switch may thus include a medium-voltage charge pump 802, and a medium-voltage level shifter 804. The self-test control signal ST(φreset) may be used to enable or disable the medium-voltage input MV of the medium-voltage charge pump 802. The medium-voltage level shifter 804 output may be used to enable or disable switch mn2 and thereby connect vddint bias to or prevent vddint bias from the pass-transistors mp0 and mp1. The non-zero bias keeps gates of the series pmoses mp0, mp1 reliably in a high-resistive mode, and ensures that the capacitive element mems_eN is left floating during the first state.
Advantageously, the medium voltage charge pump 802 is configured to consume as little current as possible. In the example of
The medium-voltage level shifter 804 output may be used to enable or disable switch mp3 and thereby to connect the high-voltage input HV as the control signal Vctrl_p to the pass-transistors mp0 and mp1, or to disable it. The switch mp3 is in a conducting state when the MV level shifter output is lower than the inverted HV level shifter output (the third state). In those situations, the high-voltage input HV becomes the control signal Vctrl_p and blocks the high-voltage input from the capacitive element (the third state). The switch mp3 also prevents vddint leaking to the HV level shifter during the first state operation.
A switch mn3 enabled and disabled by the element-specific control signal en_hvN/dis_hvN may be used to zero the control signal Vctrl_p and shift the series pmos switches mp0, mp1 to a conducting state, and thereby enable the second state of operation.
A reset transistor mn0 enabled and disabled by the element-specific control signal dis_hvN may be included to improve isolation of the high-voltage input of one capacitive element from other multiplexed capacitive elements. Furthermore, the reset transistor mn0 prevents the bulk diode of series pmos from conducting during the first state operation, i.e. when the high-voltage input HV is zero and capacitive element is in non-zero potential.
Accordingly, division of the time-discrete high-voltage to a number of capacitive elements can be controlled with a compact switching configuration and with minimal transient effects.
In some embodiments, the time-discrete high-voltage supply needs to be used with elements that have a limited gate oxide voltage tolerance, for example drain extended devices. In such cases, multiplexing of the high-voltage supply cannot be controlled with level shifters as shown in
The high-voltage input HV may be generated with the charge pump configuration of
A dashed line in the example configuration of
State
dis_hvN
en_hvN
ST(Φreset)
HV
mems_eN
Vg(mp0)
Vg(mn1)
Vg(mp2)
Vg(mn3/4/5)
1
1
0
1
vss
highZ
vddint
vss
vddint
MV
2
0
1
0
HV
HV
HV(N − x)
vss
HV(N − x)
vss
3
1
0
0
HV
vss
HV(N + y)
vddint
HV(N − x)
vss
The time-discrete approach of the present invention thus enables a streamlined and non-complex switching mechanism that can have very area optimized implementations even in multiplexed element configurations. The area optimization is achieved by taking advantage of the discrete-time nature of the readout circuitry interface. This way the charge pump reset and control scheme can be designed so that DC current load of the charge pump remains very small, while multiplexing of single charge pump output to several isolated stator electrodes is possible. Absence of large resistors in the charge pump ensures that charge pump area consumption remains low for two reasons: firstly, large resistors take considerable area and secondly, resistors consume DC current which forces to increase the area of the charge pump. The switching mechanism adapts also easily for implementations where components with limited voltage tolerances are used. This is made possible by introducing the floating charge pumps (C2, N2, N3) which allow the gate bias voltage (Vg(mp0, Vg(mp2)) of floating transistors (mp0, mp2) to be biased only the required amount below or above the output self-test bias voltage (HV) value. Typically, when only one or maximum two stages is required for these auxiliary floating charge pumps (C2, N2, N3) and load is determined by the driven gates, these floating charge pumps (C2, N2, N3) do not significantly increase the area.
It is known to be very difficult to create a precisely acceleration resembling test signal using high-voltage excitation. Instead, it is more feasible to verify using the high voltages that the proof-mass moves the required full-scale range in a specified time frame, and that the capacitive sensor returns to the condition prior to the excitation with a specified accuracy and speed after the excitation is removed. For example, it is possible to define a target deflection and stop the self-test right when this deflection is achieved by the capacitive element. The high-voltage bias may be set to be somewhat higher (10-20%) than an estimated voltage for the actual desired deflection, and the decision to stop the self-test may be made immediately when the desired deflection is achieved. The time needed to achieve the desired deflection and to return back to the zero deflection may also be used as an indication on the state of the tested capacitive element. This arrangement reduces the need for accurate high-voltage levels and thus significantly simplifies the self-test implementation.
Accordingly, in a first sub-test of the self-test of a selected capacitive element, the capability to respond to the actuation may be tested. For this, during the front end reset periods Φreset, generation of the self-test bias voltage HV is triggered (stage 1210), and switching arrangements within the capacitive sensor couples the self-test bias voltage HV to the selected capacitive element (stage 1212). This procedure may continue during the reset periods, as long as the self-test of the selected capacitive element is on.
During the corresponding front end readout periods (Φread), deflection of the tested capacitive element is detected (stage 1214). The measured data is compared (stage 1216) to a defined deflection test end condition to determine whether the first sub-test is to be ended. The end may be triggered, for example, when the measured deflection reaches a defined threshold value, or when a predefined actuation test interval is reached.
In the end of the first part, the result of the first sub-test may be recorded (stage 1218). For example, if the first sub-test ends by the measured deflection reaching the defined threshold value, the first sub-test may be considered to be successful (part1 is OK). Correspondingly, if the first sub-test ends by the actuation test interval ending before the measured deflection reaches the defined threshold value, the first sub-test may be considered to indicate failure (part1 is NOK). Alternatively, it is possible to define a target time range during which the defined threshold deflection should be reached, and record the actual time period in which the defined threshold deflection is reached. If the actual time period is not within the target time range, the first sub-test may be considered to indicate failure, even if the actuation test interval is not exceeded.
In the second sub-test of the self-test it is possible to test whether the selected capacitive element returns appropriately back to the initial condition. Accordingly, in the second sub-test of the self-test of the selected capacitive element, the self-test may again progress in alternating front end readout periods and front end reset periods (stage 1220). However, this time the switching arrangements within the capacitive sensor are configured to block the self-test bias voltage (HV) from the selected capacitive element (stage 1222). This means that there is no electrostatic force to create the deflection and the measured values should approach the initial measured values Dstart stored at the time before the actuation.
Accordingly, again during the corresponding front end readout periods Φread, the deflection of the tested capacitive element is detected (stage 1224). The measured data is compared (stage 1226) to a defined return test end condition to determine whether the second sub-test is to be ended. The end may be triggered, for example, when the measured values reach, within calibrated precision, the initial measured values Dstart, or when a predefined return test interval is reached.
In the end of the second part, the result of the second sub-test may be recorded (stage 1228). For example, if the second sub-test ends by the measured values corresponding to the initial measured values Dstart, the second sub-test may be considered to be successful (part2 is OK). Correspondingly, if the second sub-test ends by the return test interval ending before measured values reach the initial measured values Dstart, the second sub-test may be considered to indicate failure (part2 is NOK). Alternatively, it is possible to define a target time range during which the initial measured values Dstart should be reached, and record the actual time period in which the initial measured values Dstart is reached. If the actual time period is not within the target time range, the second sub-test may be considered to indicate failure, even if the return test interval is not exceeded.
After the first sub-test and the second sub-test of the self-test of the selected capacitive element, the results of the partial tests are checked, and the total result for the tested capacitive element is recorded (stage 1230). For example, the capacitive element may be considered to pass the test successfully (stage 1232), if both the first sub-test and the second sub-test are successful. Correspondingly, the capacitive element may be considered to fail the test (stage 1234), if either of the first sub-test and the second sub-test fails.
After the self-test of a selected capacitive element, it is checked whether the self-test operation is to end (stage 1236). If yes, the sensor returns to normal operation (stage 1200). If not, testing of another capacitive element may be started (stage 1204).
It is apparent to a person skilled in the art that as technology advances, the basic idea of the invention can be implemented in various ways. The invention and its embodiments are therefore not restricted to the above examples, but they may vary within the scope of the claims.
Erkkilä, Jouni, Aaltonen, Lasse
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