Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.
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1. A chip mounting structure, comprising:
a chip including an interlayer insulating layer having a low dielectric constant; and
a substrate to which the chip is flip-chip connected via a bump, the substrate having a shape of a square from which elongated cuts that extend a length e from corners of the square toward the corresponding corners of the chip are cut off, where the length e is expressed as the following expression:
e>(√{square root over (2)}−1)B wherein the elongated cuts reduce a mechanical stress exerted on the interlayer insulating layer at a corner portion of the chip due to a thermal stress, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate, wherein B denotes a distance from each of sides of the chip to a corresponding portion of the edge of the substrate.
3. A chip mounting structure, comprising:
a substrate having a shape of a square except for square portions of the substrate that are cut off at corners of the substrate, each square portion having sides of a length c;
a chip positioned at a center of the substrate, the chip being flip-chip connected to the substrate via a bump, the chip having a shape of a square, the chip including an interlayer insulating layer having a low dielectric constant;
wherein the substrate has a shape that satisfies A<B where A denotes a distance from each corner of the chip to a nearest edge of the substrate and B denotes a distance from a midpoint of each side of the chip to a midpoint of a nearest side of the substrate, and wherein the length c is expressed as the following expression
wherein the square portions that are cut off at corners of the substrate reduce a mechanical stress exerted on the interlayer insulating layer at corners of the chip due to a thermal stress, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.
4. A chip mounting structure, comprising:
a substrate having a shape of a square except for right-angled isosceles triangle portions of the substrate that are cut off at corners of the substrate, each right-angled isosceles triangle having two sides of a length d;
a chip positioned at a center of the substrate, the chip being flip-chip connected to the substrate via a bump, the chip having a shape of a square, the chip including an interlayer insulating layer having a low dielectric constant;
wherein the substrate has a shape that satisfies A<B where A denotes a distance from each corner of the chip to a nearest edge of the substrate and B denotes a distance from a midpoint of each side of the chip to a midpoint of a nearest side of the substrate, and wherein the length d is expressed as the following expression:
d>(2−√{square root over (2)})B wherein the right-angled isosceles triangle portions that are cut off at corners of the substrate reduce a mechanical stress exerted on the interlayer insulating layer at corners of the chip due to a thermal stress, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.
2. The chip mounting structure according to
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This application is based upon and claims priority from prior U.S. patent application Ser. No. 14/930,984 filed on Nov. 3, 2015, which claims priority for U.S. patent application Ser. No. 14/548,583 filed on Nov. 20, 2014, which claims priority from Japanese Patent Application Number 2013247505 filed on Nov. 29, 2013 and Japanese Patent Application Number 2013257637 filed on Dec. 13, 2013, the entire disclosure of each is hereby incorporated by reference in its entirety.
The present invention relates to a technology of mounting an integrated circuit (IC) chip (or simply “a chip”, below) on a substrate and particularly to a chip mounting structure in which a chip is mounted on a substrate having such a shape that a stress exerted on a flip-chip-connected chip is reduced.
In these years, with size reduction of semiconductor devices, the dielectric constant (k) of a material of interlayer insulators in the back end of line (BEOL) has been decreasing. However, a material of insulators having a low dielectric constant, such as SiCOH (hydroxyl silicon carbide), is porous and is thus very brittle. The interlayer insulating layer itself thus has a low mechanical strength and becomes separated due to a stress being exerted at the time of cooling after being subjected to flip chip mounting and reflow soldering.
Since a chip and a substrate on which the chip is mounted are connected together with a lead-free solder, which is harder and less ductile than a lead solder that has been used thus far, the stress exerted on the interlayer insulating layer due to a difference in coefficient of thermal expansion between the chip and the substrate has been increasing.
In addition, thinning of printed circuit boards employing, for example, organic substrates for the purpose of an improvement of electrical characteristics or a cost reduction as a result of reduction of the number of layers increases the warpage of the substrate, leading to an increase of the stress exerted on the interlayer insulating layer.
Japanese Patent Application Publication No. 5-47955 describes a support board disposed between a semiconductor device and a circuit board. Electrode terminals are disposed on the surface of the support board so as to face electrode terminals disposed on the peripheral portion of the semiconductor device. Electrode terminals electrically connected with the electrode terminals on the surface of the support board are arranged in a grid form on the back surface of the support board. The electrode terminals on the surface of the support board and the electrode terminals on the back surface of the support board are respectively connected, via bumps, with the semiconductor device and the circuit board. Thus, the stress that occurs due to a difference in coefficient of thermal expansion between the semiconductor device and the circuit board is dispersed into bumps arranged in the grid form, whereby malfunctions of a circuit device due to stress concentration are minimized.
In the technology of Patent Application Publication No. 5-47955, the stress exerted on the semiconductor device is reduced by dispersing the stress that occurs due to the difference in coefficient of thermal expansion between the semiconductor device and the circuit board into bumps arranged in the grid form on the back surface of the support board disposed between the semiconductor device and the circuit board. Since this technology involves disposition of the support board between the semiconductor device and the circuit board, an arrangement of electrode terminals on the back surface of the support board is limited to the grid form and is not allowed to be changed in accordance with the design of the circuit device.
Japanese Patent Application Publication No. 2002-100699 describes a semiconductor device in which a semiconductor chip has through-holes at corner portions and a reinforcement land having a ball bump on the connection side is formed through each through-hole. When the chip is mounted on a mounting substrate, the reinforcement lands are connected to the substrate so that the thermal stress exerted on circuit connection pads adjacent to the corners of the semiconductor chip attenuates, whereby separation or electrical disconnection of the circuit connection pads is minimized.
The technology of Japanese Patent Application Publication No. 2002-100699 involves formation of a reinforcement land at each corner portion of a semiconductor chip and occupation of an area for the reinforcement land at each corner portion of the semiconductor chip, whereby the use of the corner portions of the semiconductor chip is limited and thus the corner portions are not allowed to be used freely.
An object of the present invention is to accomplish highly reliable chip mounting by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. The object of the present invention includes to provide a chip mounting structure in which a chip is mounted on a substrate having the above-described shape. A chip mounting structure according to an embodiment of the present invention includes a chip including an interlayer insulating layer having a low dielectric constant and a substrate to which the chip is flip-chip connected via a bump, wherein the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at a corner portion of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.
Preferably, the substrate has such a shape that satisfies A<B where A denotes a distance from each of corners of the chip to a corresponding position on an edge of the substrate that is on a line extending from a center of the chip, positioned at the same position as a center of the substrate, through the corner of the chip and B denotes a distance from each of sides of the chip to a corresponding portion of the edge of the substrate, the corresponding portion being parallel to the side of the chip.
Preferably, the substrate has a shape of a square from which squares each having sides of a length c are cut off at corner portions of the square, where the length c is expressed as the following expression:
Preferably, the substrate has a shape of a square from which right-angled isosceles triangles each having two sides of a length d are cut off at corner portions of the square, where the length d is expressed as the following expression:
d>(2−√{square root over (2)})B Expression 2
Preferably, the substrate has a shape of a square from which cuts that extend a length e from the corresponding corners of the square toward the corresponding corners of the chip are cut off, where the length e is expressed as the following expression:
e>(√{square root over (2)}−1)B Expression 3.
Preferably, the substrate has a shape of a circle having a center positioned at the same position as a center of the chip and having a radius longer than a distance from the center of the chip to each of corners of the chip.
In the present invention, highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Particularly, the highly reliable chip mounting is accomplished by a chip mounting structure, in which a chip is mounted on a substrate having the above-described shape, provided through the present invention.
In a chip mounting structure according to the present invention, the stress exerted on a chip is reduced by using a substrate having a predetermined shape. Thus, unlike in the case of the technology of Japanese Patent Application Publication No. 5-47955, the chip mounting structure according to the present invention does not involve the use of an additional support board between a semiconductor device and a circuit board, whereby the production cost of the chip mounting structure can be minimized. Moreover, unlike in the case of the technology of Japanese Patent Application Publication No. 2002-100699, the chip mounting structure does not involve occupation of an area adjacent to each corner of a semiconductor chip for reinforcement, whereby the area adjacent to each corner of the chip can be effectively used.
The accompanying figures wherein reference numerals refer to identical or functionally similar elements throughout the separate views, and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention, in which:
As required, detailed embodiments are disclosed herein; however, it is to be understood that the disclosed embodiments are merely examples and that the systems and methods described below can be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present subject matter in virtually any appropriately detailed structure and function. Further, the terms and phrases used herein are not intended to be limiting, but rather, to provide an understandable description of the concepts.
The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Best modes for embodying the present invention will be illustrated below in detail with reference to the drawings. However, the present invention within the scope of claims is not limited to the following embodiments. In addition, all the combinations of the characteristics described in the embodiments are not necessarily essential to solution to problems. The present invention may be embodied in various different modes and should not be understood as being limited to the contents described in the embodiments. Throughout the entire description of the embodiments, the same components are denoted by the same reference numerals.
The inventors have studied the relationship between the shape of a substrate and a stress exerted on the chip by performing structure analysis of a chip mounting structure using, for example, a finite element method (FEM). The inventors have thus found that changing the shape of the substrate on the basis of the studied relationship reduces the stress exerted on the interlayer insulating layer through bumps at the corners of the chip.
On the basis of this finding, the inventor has developed the use of a substrate having a shape in which A<B and in which the mechanical stress exerted on the interlayer insulating layer at corner portions of the chip is reduced. Highly reliable chip mounting is accomplished by using a chip mounting structure in which a chip is mounted on a substrate having such a shape.
√{square root over (2)}B Expression 4
The length of the diagonal of the squares 510 is expressed by the following expression:
√{square root over (2)}c Expression 5
Thus, the distance A is expressed by the following expression:
A=√{square root over (2)}B−√{square root over (2)}c=√{square root over (2)}(B−c) Expression 6
Since A<B, the following expression is satisfied:
√{square root over (2)}(B−c)<B Expression 7
When this expression is changed by changing the subject to the length c, the length c is expressed by the following expression:
In order that the substrate 505 has a shape that satisfies A<B, the length c has to satisfy the above expression. For example, when the chip 205 is a 20 mm square and the original square of the substrate 505 is a 50 mm square, the distance B is 50/2−20/2, that is, 15 mm. When the distance B is 15 mm, the length c has to be longer than 4.4 mm.
√{square root over (2)}B Expression 9
The length or the height from the base to the vertex of each right-angled isosceles triangle 610 is expressed by the following expression:
Thus, the distance A is expressed by the following expression:
Since A<B, the following expression is satisfied:
When this expression is changed by changing the subject to the length d, the length d is expressed by the following expression:
d>(2−√{square root over (2)})B Expression 13
In order that the substrate 605 has a shape that satisfies A<B, the length d has to satisfy the above expression. For example, when the chip 205 is a 20 mm square and the original square of the substrate 605 is a 50 mm square, the distance B is 50/2−20/2, that is, 15 mm. When the distance B is 15 mm, the length d has to be longer than 8.8 mm.
√{square root over (2)}B Expression 14
Since the cuts having a length e are cut off at corner portions of the original square, the distance A is expressed by the following expression:
A=√{square root over (2)}B−e Expression 15
Since A<B, the following expression is satisfied:
√{square root over (2)}B−e<B Expression 16
When this expression is changed by changing the subject to the length e, the length e is expressed by the following expression:
e>(√{square root over (2)}−1)B Expression 17
In order that the substrate 705 has a shape that satisfies A<B, the length e has to satisfy the above expression. For example, when the chip 205 is a 20 mm square and the original square of the substrate 705 is a 50 mm square, the distance B is 50/2−20/2, that is, 15 mm. When the distance B is 15 mm, the length e has to be longer than 6.2 mm.
Although the present invention has been described thus far using some embodiments, the technical scope of the invention is not limited to the scope described in relation to these embodiments. The embodiments may be modified or improved in various manners and modes to which such modification or improvement has been made are also naturally included in the technical scope of the invention.
The description of the present application has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Okamoto, Keishi, Toriyama, Kazushige, Matsumoto, Keiji, Horibe, Akihiro
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