A memory interface architecture uses a serializer/deserializer (serdes) to connect a memory array on one semiconductor die to a device on another semiconductor die, for example via a fast interposer.
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16. A semiconductor die comprising:
a memory array and a serializer/deserializer (serdes), the serdes connected to the memory array, the serdes converting parallel data read out from the memory array into a serial data stream;
a device with access to the memory array;
a direct transmission path between the serdes and the device, for transmitting the serial data stream between the serdes and the device, wherein the direct transmission path terminates at the device and at the memory array; and
wherein the direct die-to-die transmission path is a non-silicon interposer, and wherein the serdes and the device are mounted to opposite sides of the non-silicon interposer.
1. A semiconductor product comprising:
a first semiconductor die including a memory array and a serializer/deserializer (serdes), the serdes connected to the memory array, the serdes converting parallel data read out from the memory array into a serial data stream;
a second semiconductor die including a device with access to the memory array;
a direct die-to-die transmission path between the first die and the second die, for transmitting the serial data stream between the first die and the second die, wherein the direct die-to-die transmission path terminates at the device and at the memory array; and
wherein the direct die-to-die transmission path is a non-silicon interposer, and wherein the first semiconductor die and the second semiconductor die are mounted to opposite sides of the non-silicon interposer.
2. The semiconductor product of
a chip package that contains the first and second die and the direct die-to-die transmission path between the first and second die.
3. The semiconductor product of
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17. The semiconductor die of
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This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application Ser. No. 62/029,759, “Communication interface architecture using serializer/deserializer,” filed Jul. 28, 2014. The subject matter of the foregoing is incorporated herein by reference in its entirety.
1. Field of the Invention
This invention relates to die-to-die communication, for example as may be used in memory applications.
2. Description of the Related Art
Communications is an important part of semiconductor devices. Consider memory as an example. Many memory interface types exist. However, memory interfaces typically use a highly parallel interface (e.g., memory bus) that is inefficient in interface width and power. That is, the memory interface typically requires a large number of pins because it is highly parallel and it typically requires a relatively large amount of power per bit of data. As applications become more memory bandwidth intensive, the total number of pins required and the total amount of power required can become prohibitively large.
Thus, there is a need for better communication architectures, including memory interface architectures.
The invention has other advantages and features which will be more readily apparent from the following detailed description of the invention and the appended claims, when taken in conjunction with the accompanying drawings, in which:
In one aspect, a memory interface architecture uses a serializer/deserializer (SerDes).
The use of direct die-to-die transmission (e.g., without having to go outside the package) with fast interposers or other types of fast connections can have many potential advantages. The SerDes can be optimized for die-to-die interconnect. Such a SerDes typically would not be sufficient for transmission off package. For example, this die-to-die approach may reduce or eliminate electrostatic discharge requirements. It can also reduce or eliminate the need for bytelane deskew (i.e., there is no need to consider skew from package to package routes on a printed circuit board). It may also reduce or eliminate pre-emphasis and equalization since the load on the SerDes can be well defined. It can also reduce the power required per bit. Because of the well-defined load, the SerDes may in some cases achieve power efficiencies of less than 1 pJ/bit, even as low as 0.3 pJ/bit or less. The higher speed SerDes can result in higher bandwidths per interface edge, for example possibly 1 terabit per second per die edge or more. A bump pitch of 80 μm or better is possible with current substrate technology. Future package capabilities may reduce this pitch. An alternate preferred approach is to eliminate the use of interposers entirely for the direct die-to-die transmission path.
The example given above was for a memory interface architecture, but this approach is not limited memory interface architectures. It can also be used in other instances, where direct die-to-die communication using SerDes might have advantage over more conventional communication schemes. The approach also is not limited to two die in a package, as shown in
The approach also is not limited to the specific architecture shown in
In yet another approach, the transmission path may be within a single die, rather than die-to-die. For example, as shown in
In another variation, the memory array is a stacked memory array (i.e., composed of multiple die stacked on top of each other). The SerDes may be implemented as part of the die on the bottom of the stack, which may also include memory controller circuitry.
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