A ball grid array (BGA) package includes a central cavity for receiving a semiconductor die therein. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically-conductive adhesive layer. bond pads on the die are electrically connected, as by wire bonds or, in the case of a flip-chip configured die, solder balls or conductive adhesive elements, to the traces. The traces are in turn, electrically connected through conductive vias to conductive element sites on the opposite side of the base laminate through a dielectric layer, the conductive element sites carrying solder balls or other discrete conductive bonding elements for connection to higher-level packaging. A ground or other reference voltage plane, which is also electrically connected to at least one trace through the anisotropically-conductive adhesive layer, may extend over the adhesive layer and frame the cavity, or also extend over the cavity to provide an enclosure for the die. In the former case, an encapsulant is applied over the die and electrical connections to the traces.
|
51. A method of manufacturing a semiconductor die package, comprising:
providing a base layer of dielectric material including at least one conductive element site on a lower surface thereof, at least one conductive via extending from said at least one conductive element site to an upper surface of said base layer, and at least one conductive trace on said upper surface of said base layer having one end electrically connected to said at least one conductive via and an opposing end; securing a dielectric layer of material to said upper surface of said base layer, said dielectric layer including at least one conductive path extending therethrough and further including a cavity extending about a die-attach area on said upper surface of said base layer, said opposing end of said at least one conductive trace extending into said cavity and terminating at a bond end adjacent said die-attach area; and securing a conductive reference plane layer to said dielectric layer, said conductive reference plane layer including an aperture therethrough extending about said cavity in said dielectric layer, said at least one conductive path electrically connecting said conductive reference plane layer to said at least one conductive via in said base layer.
1. A method of fabricating a semiconductor die package, comprising:
forming at least one conductive via extending through a base layer of dielectric material; forming at least one conductive element site on a lower surface of said base layer electrically connected to said at least one conductive via; forming at least one conductive trace on an upper surface of said base layer having one end electrically connected to said at least one conductive via and an opposing end; applying a dielectric layer of material to at least a portion of said upper surface of said base layer including at least one conductive path extending therethrough and further including a cavity extending about a die-attach area on said upper surface of said base layer, said opposing end of said at least one conductive trace extending into said cavity and terminating at a bond end adjacent said die-attach area; and applying a conductive reference plane layer to said dielectric layer, said at least one conductive path electrically connecting said conductive reference plane layer to said at least one conductive via in said base layer, said conductive reference plane layer covering at least a portion of said dielectric layer and extending about said cavity in said dielectric layer.
79. A method of making a semiconductor die package, comprising:
forming a plurality of conductive vias in a base layer of dielectric material, each conductive via of said plurality of conductive vias including a lower end terminating proximate a lower surface of said base layer and extending through said base layer to an upper end terminating proximate an upper surface of said base layer; forming a plurality of conductive element sites on said lower surface of said base layer, each conductive element site of said plurality of conductive element sites directly contacting said lower end of one conductive via of said plurality of conductive vias; forming a plurality of conductive traces on said upper surface of said base layer, each conductive trace of said plurality of conductive traces including one end directly contacting said upper end of one conductive via of said plurality of conductive vias extending to an opposing end terminating at a bond located adjacent a die-attach area on said upper surface of said base layer; applying a dielectric layer of material to at least a portion of said upper surface of said base layer, said dielectric layer including at least one conductive path extending from a lower surface thereof to an upper surface thereof and further including a cavity extending therethrough and about said die-attach area on said upper surface of said base layer; and applying a conductive reference plane layer to said upper surface of said dielectric layer electrically connected to said upper end of at least one conductive via of said plurality of conductive vias in said base layer by said at least one conductive path, said conductive reference plane layer extending about said cavity in said dielectric layer and extending over at least a portion of said upper surface of said dielectric layer.
2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
8. The method of
9. The method of
10. The method
11. The method of
12. The method of
13. The method of
14. The method of
15. The method of
forming a layer comprising nickel on said at least one conductive element site; and forming a layer comprising gold on said nickel layer.
16. The method of
17. The method of
18. The method of
forming a layer comprising nickel on said conductive die-attach pad; and forming a layer comprising gold on said nickel layer.
19. The method of
20. The method of
21. The method of
22. The method of
23. The method of
24. The method of
forming a layer comprising nickel on at least said bond end of said at least one conductive trace; and forming a layer comprising gold on said nickel layer.
25. The method of
applying a layer of conductive material to at least a portion of said lower surface of said base layer; applying a layer of photoresist material to said layer of conductive material; selectively exposing said layer of photoresist material through a mask defining a desired pattern; removing unadhered portions of photoresist material from said layer of conductive material; and chemically etching exposed portions of said layer of conductive material to form said at least one conductive element site.
26. The method of
applying a layer of conductive material to at least a portion of said upper surface of said base layer; applying a layer of photoresist material to said layer of conductive material; selectively exposing said layer of photoresist material through a mask defining a desired pattern; removing unadhered portions of said layer of photoresist material from said layer of conductive material; and chemically etching exposed portions of said layer of conductive material to form said at least one conductive trace.
27. The method
forming a hole through said base layer, said hole being defined by an interior wall; and forming a layer of conductive material on at least a portion of said interior wall of said hole.
28. The method of
29. The method of
30. The method of
31. The method of
32. The method of
33. The method of
34. The method of
35. The method of
36. The method of
37. The method of
38. The method of
attaching a semiconductor die to said die-attach area of said base layer; and electrically connecting a bond pad on said semiconductor die to said bond end of said at least one conductive trace prior to applying said conductive reference plane layer to said dielectric layer.
39. The method of 38, wherein said applying a dielectric layer of material to at least a portion of said upper surface of said base layer comprises applying a dielectric layer of a thickness sufficient to provide clearance between said semiconductor die and a plurality of bond wires extending therefrom and said conductive reference plane layer.
40. The method of
41. The method of
42. The method of
43. The method of
44. The method of
45. The method of
providing a flip-chip configured semiconductor die having a plurality of conductive elements extending from a front surface thereof and arranged in a pattern corresponding to said array of conductive pads on said base layer; and attaching said plurality of conductive elements extending from said semiconductor die to said array of conductive pads on said base layer to secure said semiconductor die to said base layer and to electrically connect each conductive element of said plurality of conductive elements to a corresponding one conductive pad of said array of conductive pads.
46. The method of
47. The method of
48. The method of
49. The method of
extending said conductive reference plane layer over said cavity in said dielectric layer to form a chamber enclosing said semiconductor die; and forming an electrical connection between said conductive reference plane layer and said back surface of said semiconductor die.
50. The method of
52. The method of
53. The method of
54. The method of
55. The method of
56. The method of
57. The method of
58. The method of
59. The method of
60. The method of
61. The method of
62. The method of
63. The method of
64. The method of
65. The method of
66. The method of
attaching a semiconductor die to said die-attach area of said base layer; and attaching a bond wire between said bond end of said at least one conductive trace and a bond pad on said semiconductor die to form an electrical connection therebetween prior to securing said conductive reference plane layer to said dielectric layer.
67. The method of
68. The method of
69. The method of
70. The method of
71. The method of
72. The method of
73. The method of
providing a semiconductor die having an array of conductive elements extending from a front surface thereof and arranged in a pattern corresponding to said terminal array on said base layer; and electrically connecting said array of conductive elements extending from said front surface of said semiconductor die to said terminal array on said base layer.
74. The method of
75. The method of
76. The method of
77. The method of
providing a conductive reference plane layer configured to extend over said cavity in said dielectric layer to form a chamber enclosing said semiconductor die; and forming an electrical connection between said conductive reference plane layer and said back surface of said semiconductor die.
78. The method of
80. The method of
providing a semiconductor die including an active surface having a plurality of bond pads thereon and an opposing back surface; securing said back surface of said semiconductor die to said die-attach area on said upper surface of said base layer with a layer of dielectric bonding agent therebetween; and electrically connecting at least one bond pad of said plurality of bond pads on said active surface of said semiconductor die to said bond end of at least one conductive trace of said plurality of conductive traces.
81. The method of
82. The method of
83. The method of
84. The method of
85. The method of
86. The method of
providing a semiconductor die including an active surface having a plurality of bond pads thereon and an opposing back surface; securing said back surface of said semiconductor die to said conductive die-attach pad on said upper surface of said base layer; and electrically connecting at least one bond pad of said plurality of bond pads on said active surface of said semiconductor die to said bond end of at least one conductive trace of said plurality of conductive traces.
87. The method of
88. The method of
89. The method of
90. The method of
91. The method of
92. The method of
|
This application is a continuation of application Ser. No. 09/146,643, filed Sep. 3, 1998, now U.S. Pat. No. 6,084,297, issued Jul. 4, 2000.
This invention relates generally to integrated circuit packages and, more particularly, to the fabrication of integrated circuit packages having multiple layers, and the resulting structure. More particularly still, the present invention relates to a fully-populated ball grid array integrated circuit package providing a cavity for mounting of a semiconductor die therein and a ground plane element extending about or optionally over the die.
In recent years, semiconductor miniaturization has resulted in the development of very large scale integrated circuit ("VLSI") devices including perhaps thousands of active components thereon. Such devices may typically be encapsulated in a protective package providing a large number of pin-outs for mounting or interconnection to external circuitry through a carrier substrate such as a printed circuit board or other higher-level packaging. The pin-outs for such packages may include, for example, a pin grid array ("PGA"), or a ball grid array ("BGA"). Both PGA and BGA packages allow for surface mounting upon a printed circuit board. PGA arrays include a two-dimensional array of metal pins that can be directly connected, as by soldering, to the printed circuit board or inserted in a mating socket arrangement carries by the board. On the other hand, a BGA array includes a two-dimensional array of conductive elements formed as, for example, balls, bumps or pillars instead of metal pins. The conductive elements may, by way of example only, be formed as solder (typically lead/tin, although other alloys are employed) balls, may each comprise a relatively higher melting point ball or bump having a solder or other relatively lower melting point outer covering, or may comprise conductive bumps or pillars formed of a conductive or conductor-filled adhesive such as an epoxy.
The bond pads of the semiconductor die disposed within a package must be connected to the printed circuit board via conductors carried by the package, either by direct contact therewith in a flip-chip orientation through conductive balls, bumps or pillars or, alternatively, by intermediate connector elements comprising wire bonds, or TAB (flexible circuit) connections. Finally, the semiconductor die is usually protected on the package by an encapsulant of a plastic, epoxy or silicone material or by being housed in a rigid-walled chamber. Exemplary BGA structures are disclosed in the following U.S. Pat. Nos. 5,397,921, 5,409,865, 5,455,456, 5,490,324, 5,563,446, 5,586,010, 5,594,275, 5,596,227, 5,598,033, 5,598,036, 5,598,321 and 5,708,567. BGA packages are offered by various manufacturers and include, among others, the Tessera μBGA, the Advanced Semiconductor Assembly Technology BGA, the Motorola PGBA (OMPAC), the Yamichi YFlex-LCP, the ProLinx VBGA™, and the IBM TBGA.
The use of BGA packages is becoming widely accepted within the industry due to the ability of BGA designs to accommodate a large number of I/Os, the number of which appears to be ever-increasing for all die types, in the relatively compact area defined within the conductive element array. However, a number of conventional BGA packages are not capable of supporting a fully populated array of conductive ball elements, as the manner in which the die is mounted in the package, or electrically connected to the package traces, requires a conductive element-devoid area in the middle of the conductive element array and so limits the number of solder balls or other conductive elements in the array.
In addition, there is a continued trend in the computer industry toward ever-higher speed integrated circuit (IC) assemblies based upon semiconductor die technology. Such high signal speeds, however, lack utility unless accompanied by suppression of system noise to an acceptable level. The trend toward lower operational signal voltages in combination with such high speeds exacerbates noise problems.
At state-of-the-art operational speeds, signal propagation delays, switching noise, and crosstalk between signal conductors resulting from mutual inductance and self inductance phenomena of the conductive paths all become significant to signal degradation. Mutual inductance results from an interaction between magnetic fields created by signal currents flowing to and from a packaged IC die through leads or traces, while self inductance results from the interaction of the foregoing fields with magnetic fields created by oppositely-directed currents flowing to and from ground.
Therefore, the integrated circuits carried on a semiconductor die would ideally be electrically connected to conductive traces on carrier substrates such as printed circuit boards and thus to other integrated circuits carried on the same or other such substrates by infinitesimally short conductors, eliminating impedance problems such as undesirable inductance and other conductor-induced system noise.
As a practical matter, however, as the capacity and speed of many integrated circuit devices such as dynamic random access memories (DRAMs) have increased, the number of inputs and outputs (I/Os) to each die has increased, requiring more numerous and complex external connections thereto and, in some instances, requiring undesirably long traces to place the bond pads serving as I/Os for the typical die in communication with the traces of the carrier substrate.
While lead inductance in IC packages has not traditionally been troublesome because slow signal frequencies of past devices render such inductance relatively insignificant, faster and ever-increasing signal frequencies of state-of-the-art electronic systems have substantially increased the practical significance of package lead or trace inductance. For example, at such faster signal frequencies, performance of IC dice using extended leads or traces for external electrical connection is slower than desirable because the inductance associated with the elongated conductive paths required slows changes in signal currents through the leads or traces, prolonging signal propagation therethrough. Further, digital signals propagating along the leads or traces are dispersing or "spreading out" because the so-called "Fourier" components of various frequencies making up the digital signals propagate through the inductance associated with the leads or traces at different speeds, causing the signal components and thus the signals themselves to disperse. While mild dispersion merely widens the digital signals without detrimental effect, severe dispersion can make the digital signals unrecognizable upon receipt. In addition, so-called "reflection" signals propagating along the leads or traces as a result of impedance mismatches between the lead fingers and associated IC die or between the leads or traces and external circuitry, caused in part by lead-associated inductance, can distort normal signals propagating concurrently with the reflection signals. Further, magnetic fields created by signal currents propagating through the lead or trace-associated inductance can induce currents in adjacent leads or traces, causing so-called "crosstalk" noise on the latter. While these various effects might be troublesome in any electronic system, the aforementioned trend toward lower voltage systems (currently 3.3 volts) and away from the traditional 5.0 volt systems increases their visibility and significance.
The ever-more-popular BGA die and package configurations described previously serve to exacerbate the noise problems by favoring a large plurality of laterally adjacent traces of substantial and varying lengths extending from adjacent a generally centralized die location to the horizontally-spaced, offset locations of vias extending to solder balls or other conductive elements for securing and electrically connecting the package to a carrier substrate. While a mechanically and electrically desirable packaging concept to accommodate the ever-increasing numbers of I/Os for state-of-the-art dice, long, varying-length, closely mutually adjacent trace runs over the package substrate become abusive in terms of unacceptably increasing real impedance as well as lead inductance (both self and mutual) in the circuit. These trace runs also increase 1) signal reflection in the circuit due to transmission line effects and degrade signal integrity due to the aforementioned, 2) propagation delays, 3) switching noise, 4) crosstalk and 5) dispersion. Further, elimination of a die-attach pad as in many BGA packages, also eliminates the potential for employing a ground plane under the die, and such a ground plane in any case would not alleviate the problems attendant to use of the long package trace runs.
Therefore, it would also be desirable for a BGA package to accommodate and substantially overcome inductance-related deficiencies so that full advantage of the beneficial aspects of the packaging concept might be realized in a relatively simple, cost-effective BGA package.
The present invention provides a BGA package supporting a fully populated array of solder balls or other conductive elements and exhibiting superior inductance characteristics.
The BGA package of the present invention comprises a base laminate or sandwich of a dielectric interposed between two conductive sheets and which, in turn, are respectively partially covered by two outer, insulative layers. One conductive sheet is patterned to provide sites for the conductive elements of an array for connecting the semiconductor die of the package to external circuitry. The other conductive sheet is patterned to define a plurality of conductive traces, each trace extending from an interior die-attach location on the laminate to a location above a conductive site, or to a location suitable for connection to a ground plane for the package. A conductive die-attach pad may be provided at the same time as the traces and communicate with a trace for providing a ground or reference voltage for the semiconductor die. Vias formed with conductive material extend from the traces on one side of the laminate through the dielectric to the conductive element sites on the opposing side. An anisotropically or "Z-axis" conductive adhesive layer in the form of a film configured as a frame is then applied over the trace side of the laminate to define and interior region cavity including the die-attach location as well as openings in the frame to allow electrical connection between a conductive stiffener for the package formed as a lid extending over the die-attach location and appropriate conductive traces. The cavity is large enough to leave inner trace ends exposed for connection of bond pads of the semiconductor die thereto by wire bonds, although the invention is not limited to this interconnection technology. For example, the inner trace ends may be patterned as a conductive pay array to connect to intermediate conductive elements such as solder balls or epoxy pillars protruding from the active surface of a flip-chip configured die placed face down on the laminate.
A ground or other voltage reference plane element (hereinafter sometimes referenced generally as a "reference plane element") is secured to the adhesive layer. Various embodiments of the structure of the BGA package of the invention include differing reference plane element structures, which in turn also permit different die enclosure techniques. In each embodiment, however, the insulative layer over the traces is provided with at least one through hole for connection of one or more circuit traces to the reference plane element by mutual contact with the anisotropically conductive adhesive layer.
In one embodiment, the reference place element is also formed as a frame of like size and shape to the adhesive frame, and placed thereover in alignment therewith, providing a deepened cavity. It should be noted that the use of a relatively thick, and thus rigid, reference plane element permits the use of a flexible, tape-type base laminate in the package, and also provides additional mass to facilitate heat transfer from the semiconductor die. After the semiconductor die is back-bonded to the die-attach location on the base laminate, connections are formed between the traces and the bond pads of the die, after which the die, inner trace ends and connections may be encapsulated with a so-called "glob top" of dielectric material, providing physical and environment protection for the encapsulated elements. The reference plane element and underlying adhesive provide a four-sided dam to prevent unwanted lateral encapsulant spread.
In another embodiment, the reference plane element comprises an imperforate conductive sheet extending over the cavity defined by the adhesive frame. If the adhesive is particularly thick, the semiconductor die relatively thin, or a recess is provided in an unusually thick dielectric portion of the base laminate, the reference plane element may be planar in nature, providing a flat lid for the cavity containing the die. If, however, the die thickness plus the height of connecting elements such as wire bonds exceeds the thickness of the adhesive frame, the reference plane element may be formed with a central dome or protrusion over the cavity area to provide adequate clearance. Such a feature may also enhance package rigidity, while permitting use of thinner conductive sheet material for the reference plane element. In this embodiment, the die is connected to the conductive traces of the base laminate before the reference plane element is applied. A thick encapsulant may again be used to protect the die and connections, but it may be preferred, in this instance, to employ a low viscosity dielectric material to merely coat the exterior of the die and the connections to prevent shorting of the latter against the inner side of the reference plane element.
As alluded to previously, yet another embodiment of the invention includes a package configured for use with a flip-chip configured semiconductor die, wherein the upper conductive sheet of the base laminate is patterned with traces having ends configured and arranged in an array of pads or terminals for contact with intermediate conductive elements, such as solder balls or conductive epoxy pillars, protruding transversely from the active surface of the die. An encapsulant may be employed to surround and in-fill between the active surface of the die and the pads, or a reference plane element employed as a lid over the cavity area to enclose the die.
FIG. 1 is a top view of one embodiment of a ball grid array package according to the present invention;
FIG. 2 is a partial cross-sectional side view of the ball grid array package according to FIG. 1;
FIG. 3 is a partial cross-sectional side view of a first variant of another embodiment of the ball grid array package of the invention;
FIG. 4 is a partial cross-sectional side view of a second variant of the embodiment of FIG. 3 of the ball grid array package of the present invention;
FIG. 5 is an enlarged partial cross-sectional side view of a flip-chip embodiment of the present invention; and
FIG. 6 is a block diagram of an electronic system incorporating the semiconductor package of the invention.
FIGS. 1 and 2 depict an exemplary ball grid array integrated circuit ("IC") package 10 having a cavity 12, shown in cross-section in FIG. 2, for receiving an integrated circuit device, such as a semiconductor die 14. In some instances, the number of elements depicted on these and the remaining drawing figures herein has been limited for clarity of illustration only, and is not intended or to be taken as a limitation on the invention as claimed.
IC package 10 includes a base laminate 16 formed of a dielectric film or sheet 18, which may comprise a polyimide such as a KAPTON® film, sandwiched between two conductive layers 20 and 22, preferably of copper, over which are located two insulative layers 6 and 8, preferably of Taiyo 9000® solder mask, although other alternative materials are suitable. The base laminate 16 may be procured as one system through Shedahl, Inc. of Northfield, Minn. as ViaThin® integrated circuit substrate. In the package 10 as illustrated, the lower conductive layer 20 has been patterned to define an exemplary 6×12 array of pad-type conductive element sites 24 (only some shown for clarity) on which a like number of conductive elements 26 for connecting die 14 to external circuitry 28 on a carrier substrate 30 (shown in broken lines in FIG. 2) are placed or formed. The copper conductive element sites 24 are preferably plated with nickel and then gold before conductive elements 26, in the form of tin/lead solder balls, are formed thereon. The upper conductive layer 22 has been patterned to define a plurality of circuit traces 32, the trace inner ends 46 of at least some of which extend from locations within cavity 12 to locations of conductive vias 34 extending through dielectric film 18 to conductive elements sites 24. Upper conductive layer 22 may also be patterned to provide a conductive die-attach pad 36, as well as traces 32 extending to the locations of vias 34 and sites 44 for connection of a ground or reference plane thereto, as hereinafter described. Die-attach pad 36 and traces 32 (or at least inner ends 46) preferably comprise a lay-up of gold over nickel over the copper of layer 22.
Patterning of the conductive layers 20 and 22 may be effected by any technique known in the art, such as application of a positive or negative photoresist, selective exposure of the resist layer through a mask to define the desired pattern followed by removal of the unfixed resist from the sheet, and chemical etching of the exposed conductive sheet material. Formation of the conductive vias 34 may be effected by 1) photo-etching, laser ablation or numerically controlled punching of apertures through the laminate structure followed by 2) electroless or electrolytic plating of a metal, preferably copper.
After conductive element sites 24 and traces 32 have been defined and conductive vias 34 formed and filled, solder mask insulative layers 6 and 8 are respectively formed over the lower and upper surfaces of the laminate. Apertures exposing conductive element sites are defined through lower solder mask layer 6, while upper solder mask layer 8 is imperforate except over die-attach pad 36 or a die attach area of the upper surface of the base laminate if no die-attach pad is employed and at locations where conductive paths of Z-axis adhesive layer 40 (see below) are to connect to vias 34 extending through base laminate 16 and connecting a conductive ground or reference plane element 50 (see below) to a conductive element site 24 and its associated conductive element 26. It should be noted that lower solder mask layer 6 defines the locations for conductive elements 26 in the form of solder balls or bumps formed or placed on conductive element sites 24 and constrains migration of the solder during reflow when the package 10 is attached to a carrier substrate 30.
A Z-axis adhesive layer 40, which may comprise Nitto ACF® anisotropic conductive film available from Nitto Denko America, Inc. of Fremont, Calif., is applied over the base laminate 16 to at least partially define cavity 12 in which die 14 will reside. As known to those of ordinary skill in the art, a "Z-axis" or anisotropically conductive adhesive comprises an adhesive or adhesively-coated dielectric or insulative film or layer having laterally-separated conductive paths 52 (some shown in broken lines) extending therethrough in an orientation transverse to the plane of the film or layer. Adhesive layer 40 is preferably applied in the form of a frame-shaped, preform sheet by which one or more traces 32 may be electrically connected to ground or reference plane element 50. Trace inner ends 46 of traces 32 extend from under adhesive layer 40 into central aperture 42 framed thereby, so that bond pads 14a of die 14 may be wire-bonded or otherwise connected as shown at 48 to the trace inner ends 46.
In the embodiment of FIGS. 1 and 2, a frame-shaped ground or reference plane element 50 having a central aperture 54 of like size and shape with central aperture 42 of adhesive layer 40 is applied over adhesive layer 40 in alignment therewith. The combined thickness of adhesive layer 40 and reference plane element 50 define the depth of cavity 12. Ground or reference plane element 50 is preferably formed of copper, and may be selected to be at least of a thickness to provide desired rigidity to package 10. Additional thickness may be incorporated in reference plane element 50 to provide a heat sink and facilitate heat transfer from die 14. Z-axis adhesive layer 40 electrically connects ground or reference plane element 50 to the upper end of a via 34 exposed through an aperture in solder mask layer 8. In fabricating package 10, a complete base laminate 16 with conductive elements 26, Z-axis adhesive layer 40 and reference plane element 50 is assembled prior to affixation of die 14 thereto.
Die 14 may then be secured to a conductive die-attach pad 36 (if used) by a conductive epoxy, silver solder, or other conductive bonding agent known in the art. If a conductive backside connection for die 14 is not required, numerous bonding agents may be employed. Further, if die 14 is secured by a dielectric adhesive, traces 32 may be patterned to extend from the edge of die 14 back under the die-attach adhesive for connection through vias 34 to underlying conductive element sites 24 to achieve the aforementioned fully-populated array of conductive elements 26. Alternatively, if a conductive die-attach pad 36 is employed, traces 24a may be patterned on the lower conductive layer 20 extending from vias 34 laterally offset from die 14 to conductive element sites 24 directly under die 14. Die 14, attached to die-attach pad 36 with a conductive bonding agent, may be connected through an appropriate via 34, conductive element site 24 and conductive element 26 typically to Vss (ground) or Vbb (back bias, or reference, potential), or even possibly to Vcc (power), depending upon the application. In the latter instance, use of a non-conductive die-attach adhesive would naturally be required. However, using die-attach pad 36 for power as suggested provides great flexibility in the number of options available for connecting power input bond pads of the die 14 to the die-attach pad 36.
Subsequent to die attach, wire bonds 48 are formed between bond pads 14a of die 14 and trace inner ends 46, using gold, aluminum, or other suitable materials as known in the art. After wire bonding is completed, a so-called "glob top" encapsulant 56 (shown for clarity in broken lines) comprising a mass of non-conductive epoxy or silicone may be applied over die 14 to fill cavity 12 to a level high enough to submerge the wire bonds 48 in encapsulant to protect the package components within cavity 12 against physical and environmental damage. It is desirable that encapsulant 56 be thermally conductive to facilitate heat transfer from die 14 during operation. A suitable thermally conductive, electrically insulative encapsulant may be a Hysol® compound, as offered by Dexter Electronic Materials of Industry, California.
Referring now to FIG. 3, another embodiment 100 of the package of the present invention is depicted. The same reference numerals are employed in FIG. 3 to identify the same features as in FIGS. 1 and 2 for clarity. Package 100 is similar to package 10, with the base laminate 16, conductive element sites 24, conductive elements 26, traces 32, solder mask insulative films 6 and 8, die-attach pad 36 (if employed) and anisotropically conductive adhesive layer 40 being configured and assembled as described with respect to package 10. It is at this juncture, differing from the assembly process for package 10, that die 14 would be attached and wire-bonded, before a ground or reference plane element 150 is affixed. The ground or reference plane element 150 of package 100 is configured as an imperforate, substantially planar sheet (again, preferably of copper) extending over cavity 12 and providing a lid therefore, the combination of adhesive layer 40 and reference plane element 150 providing an environmentally-sealed chamber 152 for die 14. In this embodiment, of course, the thickness of adhesive layer 40 may be sufficient to provide clearance for die 14 and wire bonds 48 under ground or reference plane element 150. Alternatively, reference plane element 150 may be provided with an underside recess 154 to be aligned with cavity 12. While a "glob top" encapsulant is not required in this embodiment, a low-viscosity dielectric material may be applied after wire-bonding to prevent shorting of the wire bonds 48 against the underside of reference plane element 150. Alternatively, a dielectric film 156 may be applied to the underside of reference plane element 150 in the central area wherein it extends over cavity 12.
Referring now to FIG. 4, a variation 200 of package 100 is depicted. Package 200 and its assembly process flow are similar to that of package 100, and the same reference numerals are used in FIG. 4 to identify the same features present in FIGS. 1-3. Ground or reference plane 250 of package 200, rather than being planar, includes a central done or protrusion 260 defining a recess 254 thereunder, which is located to be above cavity 12 in assembled package 200 and thus define an environmentally-sealed chamber 252 of enhanced height to clear die 14 and wire bonds 48. Such a configuration may be required to accommodate an unusually thick die or excessive wire bond height. Again, a dielectric film 256 may be formed on the underside of element 250 to preclude wire bond shorting, or a dielectric coating may be applied to the wire bonds 48.
In the embodiment of FIG. 5, a flip-chip configured die 14 is carried in package 300, only the die cavity 12 portion of which is depicted for clarity, all other aspects of package 300 corresponding to the structure of one or more of the previously-described packages 10, 100 or 200. The same reference numerals are used in FIG. 5 to identify the same features present in FIGS. 1 through 4. In package 300, die-attach pad 36 is eliminated and base laminate 16 includes traces 32 extending into cavity 12 defined by central aperture 42 of adhesive layer 40 and terminating at trace inner ends 46 sized, shaped and located to define a terminal array 302 configured to connect to intermediate conductive elements 126 extending transversely from active surface 14as of a flip-chip configured die 14. Conductive elements 126 may comprise solder, or a conductive- or conductor-carrying adhesive. Reference plane element 50 may surround cavity 12 as shown, or extend thereover as shown in broken lines at 50a. In the former instance, a connection between the backside 14b of die 14 and the reference plane element 50 may be effected by a wire or strap 51 (which may even comprise a protrusion of the reference plane material over central aperture 42), while in the latter instance, a conductive material such as a conductive epoxy or silver solder or even a resilient conductive element may be interposed between the backside 14b of the die and the underside of the reference plane element 50, such interposed structures shown in broken lines and generally designated by reference numeral 53 in FIG. 5.
In all its embodiments, the present invention comprises a packaged semiconductor device wherein inductance and impedance of a group of adjacent, substantially co-planar circuit traces is reduced, and reflection and signal integrity improved, through the use of at least one voltage reference plane element in close, overlapping or superimposed proximity to the plane of the traces. As noted above, while in many, if not most, instances the voltage potential will be connected to ground, or Vss, it is contemplated that there are some applications where another reference potential may be employed with the plane element.
The reference plane element of the present invention reduces the self inductance associated with closely-adjacent, elongated traces by reducing the magnetic flux caused by oppositely directed currents flowing in the traces and the reference plane element, typically ground. The reference plane element reduces the self inductance through an increase in effective width and a decrease in the distance between the voltage reference plane and the traces. Similarly, the immediate proximity of the reference plane element to closely laterally adjacent traces of the base laminate exhibiting troublesome inductance characteristics reduces mutual inductance by interruption of the magnetic fields generated by adjacent traces and thus the effects of their interaction. As a result of the presence of the reference plane element in the package, circuit switching times are reduced while noise is maintained at a tolerable level.
The voltage reference plane arrangement of the invention also provides at least a nominal heat sink effect to the semiconductor device as housed in the central cavity of the package, promoting more even distribution of heat generated during operation of the semiconductor die than might be achieved through the traces alone. As noted above, the heat sink effect may, of course, be enhanced by increasing the mass of the reference plane element, as by enhancing its thickness within the constraints of the package dimensions. A further advantage of the present invention resides in the bending and torsional rigidity, mechanical support and protection provided the traces, the base laminate and the package as a whole by the reference plane element.
Those skilled in the art will appreciate that semiconductor dice usable with packages according to the present invention may comprise an integrated circuit die 14 employed for storing or processing digital information, including, for example, a Dynamic Random Access Memory (DRAM) integrated circuit die, a Static Random Access Memory (SRAM) integrated circuit die, a Synchronous Graphics Random Access Memory (SGRAM) integrated circuit die, a Programmable Read-Only Memory (PROM) integrated circuit die, an Electrically Erasable PROM (EEPROM) integrated circuit die, a flash memory die and a microprocessor die, and that the present invention includes such devices within its scope. In addition, it will be understood that the shape size, and configuration of dice and bond pads thereon may be varied without departing from the scope of the invention and appended claims.
As shown in FIG. 6, an electronic system 400 includes an input device 402 and an output device 404 coupled to a processor device 406 which, in turn, is coupled to a memory device 408, at least one of the processor device 406 and the memory device 408 being configured as one of the exemplary integrated circuit packages 10, 100, 200 or 300 according to the invention.
Although the invention has been described in detail, it should be realized that certain modifications can be made within the scope and spirit of the invention by those skilled in the art. For example, although less preferred, in lieu of an anisotropic adhesive layer, an insulative layer defining one or more suitably-placed apertures therethrough housing conductive materials may be employed to connect the ground or reference plane element to a trace on the base laminate, to a via therethrough and ultimately to higher-level packaging through a conductive element on the bottom of the base laminate. In such an arrangement, the upper insulative film may be eliminated. Conductive elements other than solder may be employed, and other materials may be substituted for those disclosed for use in the various other structural features of the invention. Therefore, the invention should be limited only by the following claims.
Brooks, Jerry M., Thummel, Steven G.
Patent | Priority | Assignee | Title |
10014240, | Mar 29 2012 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Embedded component package and fabrication method |
10090228, | Mar 06 2012 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device with leadframe configured to facilitate reduced burr formation |
10163826, | Mar 13 2007 | Micron Technology, Inc. | Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices |
10211114, | Feb 28 2006 | Micron Technology, Inc. | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
10410967, | Nov 29 2011 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Electronic device comprising a conductive pad on a protruding-through electrode |
10546833, | Dec 07 2009 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Method of forming a plurality of electronic component packages |
10566310, | Apr 11 2016 | Invensas Corporation | Microelectronic packages having stacked die and wire bond interconnects |
10665567, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Wafer level package and fabrication method |
10692827, | Mar 13 2007 | Micron Technology, Inc. | Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices |
10811341, | Jan 05 2009 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device with through-mold via |
11043458, | Nov 29 2011 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Method of manufacturing an electronic device comprising a conductive pad on a protruding-through electrode |
11553600, | Dec 26 2019 | Samsung Display Co., Ltd. | Device for manufacturing conductive film |
11869829, | Jan 05 2009 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD. | Semiconductor device with through-mold via |
6469897, | Jan 30 2001 | Siliconware Precision Industries Co., Ltd. | Cavity-down tape ball grid array package assembly with grounded heat sink and method of fabricating the same |
6486545, | Jul 26 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Pre-drilled ball grid array package |
6525553, | Sep 11 2000 | STATS CHIPPAC PTE LTE | Ground pin concept for singulated ball grid array |
6534391, | Aug 17 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package having substrate with laser-formed aperture through solder mask layer |
6544812, | Nov 06 2000 | STATS CHIPPAC PTE LTE ; STATS CHIPPAC PTE LTD | Single unit automated assembly of flex enhanced ball grid array packages |
6545345, | Mar 20 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Mounting for a package containing a chip |
6548759, | Jun 28 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Pre-drilled image sensor package |
6558600, | May 04 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method for packaging microelectronic substrates |
6564979, | Jul 18 2001 | Micron Technology, Inc. | Method and apparatus for dispensing adhesive on microelectronic substrate supports |
6571468, | Feb 26 2001 | SATURN ELECTRONICS & ENGINEERING TUSTIN , INC ; IMI USA, INC | Traceless flip chip assembly and method |
6576494, | Jun 28 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Recessed encapsulated microelectronic devices and methods for formation |
6621163, | Nov 09 2000 | Qorvo US, Inc | Electronic device having an electronic component with a multi-layer cover, and method |
6622380, | Feb 12 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods for manufacturing microelectronic devices and methods for mounting microelectronic packages to circuit boards |
6638595, | Jun 28 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for reduced flash encapsulation of microelectronic devices |
6644949, | Jun 28 2000 | Micron Technology, Inc. | Apparatus for reduced flash encapsulation of microelectronic devices |
6653173, | Jun 16 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for packaging a microelectronic die |
6656769, | May 08 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for distributing mold material in a mold for packaging microelectronic devices |
6657864, | Dec 16 2002 | GLOBALFOUNDRIES U S INC | High density thermal solution for direct attach modules |
6660559, | Jun 25 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Method of making a chip carrier package using laser ablation |
6664139, | Jun 16 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for packaging a microelectronic die |
6677675, | Jun 16 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic devices and microelectronic die packages |
6683388, | Jun 16 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for packaging a microelectronic die |
6730536, | Jun 28 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Pre-drilled image sensor package fabrication method |
6740546, | Aug 21 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic devices and methods for assembling microelectronic devices |
6750545, | Feb 28 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package capable of die stacking |
6777789, | Mar 20 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Mounting for a package containing a chip |
6781066, | Aug 19 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic component assemblies |
6794740, | Mar 13 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Leadframe package for semiconductor devices |
6796028, | Aug 23 2000 | Micron Technology, Inc. | Method of Interconnecting substrates for electrical coupling of microelectronic components |
6798047, | Dec 26 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Pre-molded leadframe |
6818973, | Sep 09 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Exposed lead QFP package fabricated through the use of a partial saw process |
6819003, | Jun 28 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Recessed encapsulated microelectronic devices and methods for formation |
6836009, | Aug 08 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic components |
6838760, | Aug 28 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic devices with interconnecting units |
6841423, | Jun 28 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods for formation of recessed encapsulated microelectronic devices |
6844615, | Mar 13 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Leadframe package for semiconductor devices |
6846701, | Feb 26 2001 | SATURN ELECTRONICS & ENGINEERING TUSTIN , INC ; IMI USA, INC | Traceless flip chip assembly and method |
6846704, | Mar 27 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package and method for manufacturing the same |
6853202, | Jan 23 2002 | MONTEREY RESEARCH, LLC | Non-stick detection method and mechanism for array molded laminate packages |
6873032, | Apr 04 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Thermally enhanced chip scale lead on chip semiconductor package and method of making same |
6873041, | Nov 07 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Power semiconductor package with strap |
6876066, | Aug 29 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic devices and methods of forming same |
6876068, | Sep 09 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package with increased number of input and output pins |
6879034, | May 01 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package including low temperature co-fired ceramic substrate |
6879050, | Feb 11 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic devices and methods for packaging microelectronic devices |
6893900, | Jun 24 1998 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Method of making an integrated circuit package |
6897550, | Jun 11 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Fully-molded leadframe stand-off feature |
6919620, | Sep 17 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Compact flash memory card with clamshell leadframe |
6921860, | Mar 18 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic component assemblies having exposed contacts |
6921967, | Sep 24 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Reinforced die pad support structure |
6921969, | Dec 24 2001 | ABB Research Ltd. | Semiconductor module and method of producing a semiconductor module |
6924550, | Aug 21 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic devices and methods for assembling microelectronic devices |
6933170, | Aug 19 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic component assemblies |
6943450, | Aug 29 2001 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic devices and methods of forming same |
6951982, | Nov 22 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic component assemblies |
6953988, | Mar 25 2000 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package |
6965157, | Nov 09 1999 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package with exposed die pad and body-locking leadframe |
6965159, | Sep 19 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Reinforced lead-frame assembly for interconnecting circuits within a circuit module |
6967395, | Mar 20 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Mounting for a package containing a chip |
6977436, | Feb 14 2002 | Macronix International Co. Ltd. | Semiconductor packaging device |
6979595, | Aug 24 2000 | Micron Technology, Inc. | Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices |
6982386, | Aug 23 2000 | Micron Technology, Inc. | Interconnecting substrates for electrical coupling of microelectronic components |
6983551, | Aug 23 2000 | Micron Technology, Inc. | Interconnecting substrates for electrical coupling of microelectronic components |
6995459, | Sep 09 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package with increased number of input and output pins |
6998702, | Sep 19 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Front edge chamfer feature for fully-molded memory cards |
7001799, | Mar 13 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Method of making a leadframe for semiconductor devices |
7005326, | Jun 24 1998 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Method of making an integrated circuit package |
7008825, | May 27 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Leadframe strip having enhanced testability |
7030474, | Jun 24 1998 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Plastic integrated circuit package and method and leadframe for making the package |
7045396, | Dec 16 1999 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Stackable semiconductor package and method for manufacturing same |
7045882, | Dec 29 2000 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package including flip chip |
7045883, | Apr 04 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Thermally enhanced chip scale lead on chip semiconductor package and method of making same |
7049685, | Aug 24 2000 | Micron Technology, Inc. | Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices |
7057268, | Jan 27 2004 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Cavity case with clip/plug for use on multi-media card |
7057280, | Nov 20 1998 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Leadframe having lead locks to secure leads to encapsulant |
7057281, | Mar 04 2003 | Micron Technology Inc. | Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths |
7061085, | Sep 19 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Semiconductor component and system having stiffener and circuit decal |
7064009, | Apr 04 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Thermally enhanced chip scale lead on chip semiconductor package and method of making same |
7067905, | Aug 08 2002 | Micron Technology, Inc. | Packaged microelectronic devices including first and second casings |
7071541, | Jun 24 1998 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Plastic integrated circuit package and method and leadframe for making the package |
7091064, | Apr 04 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for attaching microelectronic substrates and support members |
7091594, | Jan 28 2004 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Leadframe type semiconductor package having reduced inductance and its manufacturing method |
7095103, | May 01 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Leadframe based memory card |
7101737, | Aug 28 2000 | Micron Technology, Inc. | Method of encapsulating interconnecting units in packaged microelectronic devices |
7102208, | Oct 15 1999 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Leadframe and semiconductor package with improved solder joint strength |
7109588, | Apr 04 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for attaching microelectronic substrates and support members |
7112474, | Jun 24 1998 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Method of making an integrated circuit package |
7115445, | Oct 15 1999 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package having reduced thickness |
7115982, | Sep 19 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Semiconductor component having stiffener, stacked dice and circuit decals |
7122905, | Feb 12 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic devices and methods for mounting microelectronic packages to circuit boards |
7138707, | Oct 21 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package including leads and conductive posts for providing increased functionality |
7144517, | Nov 07 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Manufacturing method for leadframe and for semiconductor package using the leadframe |
7157310, | Sep 01 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods for packaging microfeature devices and microfeature devices formed by such methods |
7170150, | Mar 27 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Lead frame for semiconductor package |
7183630, | Apr 15 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Lead frame with plated end leads |
7190062, | Jun 15 2004 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Embedded leadframe semiconductor package |
7192807, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Wafer level package and fabrication method |
7195957, | Aug 08 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic components |
7202554, | Aug 19 2004 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package and its manufacturing method |
7211471, | Sep 09 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Exposed lead QFP package fabricated through the use of a partial saw process |
7211879, | Nov 12 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package with chamfered corners and method of manufacturing the same |
7214326, | Nov 07 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Increased capacity leadframe and semiconductor package using the same |
7217991, | Oct 22 2004 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Fan-in leadframe semiconductor package |
7218001, | Oct 31 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Reduced footprint packaged microelectronic components and methods for manufacturing such microelectronic components |
7245007, | Sep 18 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Exposed lead interposer leadframe package |
7247523, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Two-sided wafer escape package |
7250328, | Jul 23 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic component assemblies with recessed wire bonds and methods of making same |
7253503, | Nov 05 1999 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Integrated circuit device packages and substrates for making the packages |
7259451, | Aug 29 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Invertible microfeature device packages |
7268018, | Sep 19 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method for fabricating semiconductor component with stiffener and circuit decal |
7268067, | Apr 15 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Semiconductor integrated circuit package having electrically disconnected solder balls for mounting |
7273769, | Aug 16 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for removing encapsulating material from a packaged microelectronic device |
7276802, | Apr 15 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Semiconductor integrated circuit package having electrically disconnected solder balls for mounting |
7306974, | Aug 08 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic devices and methods for manufacturing and operating packaged microelectronic device assemblies |
7321162, | Oct 15 1999 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package having reduced thickness |
7332375, | Jun 24 1998 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Method of making an integrated circuit package |
7332376, | Aug 28 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method of encapsulating packaged microelectronic devices with a barrier |
7335978, | Sep 19 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Semiconductor component having stiffener, circuit decal and terminal contacts |
7342319, | Apr 15 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Semiconductor integrated circuit package having electrically disconnected solder balls for mounting |
7345807, | Dec 29 2000 | Texas Instruments Incorporated | Laminated package |
7356782, | Feb 06 2002 | VIA Technologies, Inc. | Voltage reference signal circuit layout inside multi-layered substrate |
7361533, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Stacked embedded leadframe |
7365424, | Jul 23 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic component assemblies with recessed wire bonds and methods of making same |
7368810, | Aug 29 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Invertible microfeature device packages |
7391104, | Jan 23 2002 | MONTEREY RESEARCH, LLC | Non-stick detection method and mechanism for array molded laminate packages |
7405487, | Aug 16 2000 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for removing encapsulating material from a packaged microelectronic device |
7420272, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Two-sided wafer escape package |
7425470, | Mar 04 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths |
7468559, | Apr 15 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Semiconductor integrated circuit package having electrically disconnected solder balls for mounting |
7473584, | Oct 22 2004 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Method for fabricating a fan-in leadframe semiconductor package |
7485952, | Sep 19 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Drop resistant bumpers for fully molded memory cards |
7507603, | Dec 02 2005 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Etch singulated semiconductor package |
7518237, | Feb 08 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microfeature systems including adhered microfeature workpieces and support members |
7521294, | Mar 27 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Lead frame for semiconductor package |
7535085, | Oct 15 1999 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package having improved adhesiveness and ground bonding |
7560804, | Jun 24 1998 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Integrated circuit package and method of making the same |
7564122, | Nov 20 1998 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant |
7572681, | Dec 08 2005 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Embedded electronic component package |
7579684, | Sep 01 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods for packing microfeature devices and microfeature devices formed by such methods |
7598598, | Feb 05 2003 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Offset etched corner leads for semiconductor package |
7615871, | Apr 04 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for attaching microelectronic substrates and support members |
7670877, | Jan 10 2005 | Lockheed Martin Corporation | Reliability enhancement process |
7671459, | Feb 08 2006 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
7687893, | Dec 27 2006 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package having leadframe with exposed anchor pads |
7687899, | Aug 07 2007 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Dual laminate package structure with embedded elements |
7691680, | Mar 04 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method of fabricating microelectronic component assemblies employing lead frames having reduced-thickness inner lengths |
7691726, | Oct 31 2003 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Reduced footprint packaged microelectronic components and methods for manufacturing such microelectronic components |
7692286, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Two-sided fan-out wafer escape package |
7696003, | Jul 23 2004 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic component assemblies with recessed wire bonds and methods of making same |
7714431, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Electronic component package comprising fan-out and fan-in traces |
7719108, | Jan 10 2005 | Lockheed Martin Corporation | Enhanced reliability semiconductor package |
7723210, | Nov 29 2005 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Direct-write wafer level chip scale package |
7723852, | Jan 21 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Stacked semiconductor package and method of making same |
7732899, | Dec 02 2005 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Etch singulated semiconductor package |
7745944, | Aug 31 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts |
7759221, | Dec 29 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods for packaging microelectronic devices and microelectronic devices formed using such methods |
7768135, | Apr 17 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package with fast power-up cycle and method of making same |
7777351, | Oct 01 2007 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Thin stacked interposer package |
7807505, | Aug 30 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods |
7808084, | May 06 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package with half-etched locking features |
7829990, | Jan 18 2007 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Stackable semiconductor package including laminate interposer |
7833456, | Feb 23 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece |
7843643, | Dec 29 2000 | Texas Instruments Incorporated | Laminated micromirror package |
7847386, | Nov 05 2007 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Reduced size stacked semiconductor package and method of making the same |
7847392, | Sep 30 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device including leadframe with increased I/O |
7851907, | Apr 15 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Semiconductor integrated circuit package having electrically disconnected solder balls for mounting |
7872343, | Aug 07 2007 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Dual laminate package structure with embedded elements |
7875963, | Nov 21 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device including leadframe having power bars and increased I/O |
7902660, | May 24 2006 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Substrate for semiconductor device and manufacturing method thereof |
7906855, | Jan 21 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Stacked semiconductor package and method of making same |
7910385, | May 12 2006 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method of fabricating microelectronic devices |
7928542, | Mar 27 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Lead frame for semiconductor package |
7932595, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Electronic component package comprising fan-out traces |
7955898, | Mar 13 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices |
7956453, | Jan 16 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package with patterning layer and method of making same |
7960818, | Mar 04 2009 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Conformal shield on punch QFN semiconductor package |
7968998, | Jun 21 2006 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
7977163, | Dec 08 2005 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Embedded electronic component package fabrication method |
7977774, | Jul 10 2007 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Fusion quad flat semiconductor package |
7982297, | Mar 06 2007 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same |
7982298, | Dec 03 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Package in package semiconductor device |
7989933, | Oct 06 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Increased I/O leadframe and semiconductor device including same |
8008758, | Oct 27 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device with increased I/O leadframe |
8026589, | Feb 23 2009 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Reduced profile stackable semiconductor package |
8058715, | Jan 09 2009 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Package in package device for RF transceiver module |
8067821, | Apr 10 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Flat semiconductor package with half package molding |
8072050, | Nov 18 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device with increased I/O leadframe including passive device |
8084867, | Jun 29 2006 | Intel Corporation | Apparatus, system, and method for wireless connection in integrated circuit packages |
8084868, | Apr 17 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package with fast power-up cycle and method of making same |
8089141, | Dec 27 2006 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package having leadframe with exposed anchor pads |
8089145, | Nov 17 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device including increased capacity leadframe |
8089159, | Oct 03 2007 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package with increased I/O density and method of making the same |
8102037, | Mar 27 2001 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Leadframe for semiconductor package |
8119455, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Wafer level package fabrication method |
8125064, | Jul 28 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Increased I/O semiconductor package and method of making same |
8138613, | May 12 2006 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic devices |
8178978, | Mar 12 2008 | VERTICAL CIRCUITS ASSIGNMENT FOR THE BENEFIT OF CREDITORS , LLC | Support mounted electrically interconnected die assembly |
8184453, | Jul 31 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Increased capacity semiconductor package |
8188579, | Nov 21 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device including leadframe having power bars and increased I/O |
8188584, | Nov 26 2005 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Direct-write wafer level chip scale package |
8202754, | Mar 29 2006 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic devices recessed in support member cavities, and associated methods |
8203213, | Dec 29 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods for packaging microelectronic devices and microelectronic devices formed using such methods |
8227921, | Oct 03 2007 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package with increased I/O density and method of making same |
8278751, | Feb 08 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods of adhering microfeature workpieces, including a chip, to a support member |
8283767, | Aug 07 2007 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Dual laminate package structure with embedded elements |
8294276, | May 27 2010 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device and fabricating method thereof |
8298866, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Wafer level package and fabrication method |
8299602, | Sep 30 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device including leadframe with increased I/O |
8304866, | Jul 10 2007 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Fusion quad flat semiconductor package |
8318287, | Jun 24 1998 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Integrated circuit package and method of making the same |
8319332, | Aug 31 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts |
8319338, | Oct 01 2007 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Thin stacked interposer package |
8324511, | Apr 06 2010 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Through via nub reveal method and structure |
8390130, | Jan 06 2011 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Through via recessed reveal structure and method |
8410585, | Apr 27 2000 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Leadframe and semiconductor package made using the leadframe |
8432023, | Oct 06 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Increased I/O leadframe and semiconductor device including same |
8440554, | Aug 02 2010 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Through via connected backside embedded circuit features structure and method |
8441110, | Jun 21 2006 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
8441132, | Mar 29 2006 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic devices recessed in support member cavities, and associated methods |
8450839, | Feb 28 2006 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
8486764, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Wafer level package and fabrication method |
8487420, | Dec 08 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Package in package semiconductor device with film over wire |
8487445, | Oct 05 2010 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device having through electrodes protruding from dielectric layer |
8501543, | Nov 29 2005 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Direct-write wafer level chip scale package |
8513108, | Jun 29 2006 | Intel Corporation | Apparatus, system, and method for wireless connection in integrated circuit packages |
8552548, | Nov 29 2011 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Conductive pad on protruding through electrode semiconductor device |
8558365, | Jan 09 2009 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Package in package device for RF transceiver module |
8575742, | Apr 06 2009 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device with increased I/O leadframe including power bars |
8629543, | Jun 11 2007 | VERTICAL CIRCUITS SOLUTIONS, INC | Electrically interconnected stacked die assemblies |
8637973, | Aug 08 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic components with terminals exposed through encapsulant |
8648450, | Jan 27 2011 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device including leadframe with a combination of leads and lands |
8674485, | Dec 08 2010 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device including leadframe with downsets |
8680656, | Jan 05 2009 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Leadframe structure for concentrated photovoltaic receiver package |
8691632, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Wafer level package and fabrication method |
8703599, | Aug 31 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts |
8704379, | Sep 10 2007 | Invensas Corporation | Semiconductor die mount by conformal die coating |
8704380, | Aug 30 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods |
8710649, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Wafer level package and fabrication method |
8723332, | Jun 11 2007 | VERTICAL CIRCUITS SOLUTIONS, INC | Electrically interconnected stacked die assemblies |
8729682, | Mar 04 2009 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Conformal shield on punch QFN semiconductor package |
8729710, | Jan 16 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package with patterning layer and method of making same |
8772947, | Dec 29 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Methods for packaging microelectronic devices and microelectronic devices formed using such methods |
8791501, | Dec 03 2010 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Integrated passive device structure and method |
8792179, | Dec 29 2000 | Texas Instruments Incorporated | Laminated micromirror package |
8796561, | Oct 05 2009 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Fan out build up substrate stackable package and method |
8823152, | Oct 27 2008 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device with increased I/O leadframe |
8853836, | Jun 24 1998 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Integrated circuit package and method of making the same |
8866272, | Mar 13 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices |
8884403, | Jun 19 2008 | Invensas Corporation | Semiconductor die array structure |
8900995, | Oct 05 2010 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device and manufacturing method thereof |
8912661, | Nov 04 2009 | Invensas Corporation | Stacked die assembly having reduced stress electrical interconnects |
8937381, | Dec 03 2009 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Thin stackable package and method |
8952522, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Wafer level package and fabrication method |
8963301, | Jun 24 1998 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Integrated circuit package and method of making the same |
8963333, | Jun 29 2006 | Intel Corporation | Apparatus, system, and method for wireless connection in integrated circuit packages |
8975745, | Jun 13 2006 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic devices recessed in support member cavities, and associated methods |
8981572, | Nov 29 2011 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Conductive pad on protruding through electrode semiconductor device |
8981573, | Jun 29 2006 | Intel Corporation | Apparatus, system, and method for wireless connection in integrated circuit packages |
9048298, | Mar 29 2012 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Backside warpage control structure and fabrication method |
9054117, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Wafer level package and fabrication method |
9064973, | Feb 08 2005 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Die attached to a support member by a plurality of adhesive members |
9082833, | Jan 06 2011 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Through via recessed reveal structure and method |
9129943, | Mar 29 2012 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Embedded component package and fabrication method |
9147583, | Oct 27 2009 | Invensas Corporation | Selective die electrical insulation by additive process |
9153517, | May 19 2010 | Invensas Corporation | Electrical connector between die pad and z-interconnect for stacked die assemblies |
9159672, | Aug 02 2010 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Through via connected backside embedded circuit features structure and method |
9184118, | May 02 2013 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Micro lead frame structure having reinforcing portions and method |
9184148, | Oct 24 2013 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package and method therefor |
9224676, | Jun 24 1998 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Integrated circuit package and method of making the same |
9252116, | Sep 10 2007 | Invensas Corporation | Semiconductor die mount by conformal die coating |
9275939, | Jan 27 2011 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device including leadframe with a combination of leads and lands and method |
9305862, | Mar 12 2008 | Invensas Corporation | Support mounted electrically interconnected die assembly |
9324614, | Apr 06 2010 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Through via nub reveal method and structure |
9360644, | Sep 08 2014 | International Business Machines Corporation | Laser die and photonics die package |
9362141, | Feb 28 2006 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
9362210, | Apr 27 2000 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Leadframe and semiconductor package made using the leadframe |
9385094, | Jun 29 2006 | Intel Corporation | Apparatus, system, and method for wireless connection in integrated circuit packages |
9406645, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Wafer level package and fabrication method |
9418872, | Aug 08 2002 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic components |
9431323, | Nov 29 2011 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Conductive pad on protruding through electrode |
9490195, | Jul 17 2015 | Invensas Corporation | Wafer-level flipped die stacks with leadframes or metal foil interconnects |
9490230, | Oct 27 2009 | Invensas Corporation | Selective die electrical insulation by additive process |
9508631, | Jan 27 2011 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device including leadframe with a combination of leads and lands and method |
9508689, | May 19 2010 | Invensas Corporation | Electrical connector between die pad and z-interconnect for stacked die assemblies |
9508691, | Dec 16 2015 | Invensas Corporation | Flipped die stacks with multiple rows of leadframe interconnects |
9543235, | Oct 22 2014 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor package and method therefor |
9595511, | May 12 2016 | Invensas Corporation | Microelectronic packages and assemblies with improved flyby signaling operation |
9631481, | Jan 27 2011 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device including leadframe with a combination of leads and lands and method |
9666513, | Jul 17 2015 | Invensas Corporation | Wafer-level flipped die stacks with leadframes or metal foil interconnects |
9673122, | May 02 2014 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Micro lead frame structure having reinforcing portions and method |
9691734, | Dec 07 2009 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Method of forming a plurality of electronic component packages |
9704725, | Mar 06 2012 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device with leadframe configured to facilitate reduced burr formation |
9728524, | Jun 30 2016 | Invensas Corporation | Enhanced density assembly having microelectronic packages mounted at substantial angle to board |
9768121, | Feb 28 2006 | Micron Technology, Inc. | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
9812415, | Mar 13 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices |
9824999, | Sep 10 2007 | Invensas Corporation | Semiconductor die mount by conformal die coating |
9825002, | Jul 17 2015 | Invensas Corporation | Flipped die stack |
9837340, | Jun 29 2009 | Intel Corporation | Apparatus, system, and method for wireless connection in integrated circuit packages |
9859257, | Dec 16 2015 | Invensas Corporation | Flipped die stacks with multiple rows of leadframe interconnects |
9871015, | Nov 08 2002 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Wafer level package and fabrication method |
9871019, | Jul 17 2015 | Invensas Corporation | Flipped die stack assemblies with leadframe interconnects |
9947623, | Nov 29 2011 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device comprising a conductive pad on a protruding-through electrode |
9978695, | Jan 27 2011 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Semiconductor device including leadframe with a combination of leads and lands and method |
Patent | Priority | Assignee | Title |
3697666, | |||
4410927, | Jan 21 1982 | Advanced Technology Interconnect Incorporated | Casing for an electrical component having improved strength and heat transfer characteristics |
4542259, | Sep 19 1984 | Olin Corporation | High density packages |
4761518, | Jan 20 1987 | Olin Corporation | Ceramic-glass-metal packaging for electronic components incorporating unique leadframe designs |
4831212, | May 09 1986 | Nissin Electric Company, Limited | Package for packing semiconductor devices and process for producing the same |
5397921, | Sep 03 1993 | UTAC Hong Kong Limited | Tab grid array |
5409865, | Oct 03 1993 | UTAC Hong Kong Limited | Process for assembling a TAB grid array package for an integrated circuit |
5455456, | Sep 15 1993 | LSI Logic Corporation | Integrated circuit package lid |
5490324, | Sep 15 1993 | LSI Logic Corporation | Method of making integrated circuit package having multiple bonding tiers |
5529959, | Jun 23 1992 | Sony Corporation | Charge-coupled device image sensor |
5563446, | Jan 25 1994 | Invensas Corporation | Surface mount peripheral leaded and ball grid array package |
5586010, | Mar 13 1995 | HOPKINS MANUFACTURING CORPORATION | Low stress ball grid array package |
5594275, | Nov 18 1993 | SAMSUG ELECTRONICS CO , LTD | J-leaded semiconductor package having a plurality of stacked ball grid array packages |
5596227, | Sep 01 1994 | Yamaha Corporation | Ball grid array type semiconductor device |
5598033, | Oct 16 1995 | Advanced Micro Devices, Inc. | Micro BGA stacking scheme |
5598036, | Jun 15 1995 | TRANSPACIFIC IP I LTD | Ball grid array having reduced mechanical stress |
5598321, | Sep 11 1995 | National Semiconductor Corporation | Ball grid array with heat sink |
5708567, | Nov 15 1995 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Ball grid array semiconductor package with ring-type heat sink |
5763939, | Sep 30 1994 | NEC Electronics Corporation | Semiconductor device having a perforated base film sheet |
5896276, | Aug 31 1994 | NEC Corporation | Electronic assembly package including connecting member between first and second substrates |
5909058, | Sep 25 1996 | Kabushiki Kaisha Toshiba | Semiconductor package and semiconductor mounting part |
5943558, | Sep 23 1996 | MEDIANA ELECTRONICS CO , LTD | Method of making an assembly package having an air tight cavity and a product made by the method |
6117705, | Apr 18 1997 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate |
6150193, | Oct 31 1996 | AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD | RF shielded device |
6168970, | Aug 01 1990 | ENTORIAN GP LLC; ENTORIAN TECHNOLOGIES INC | Ultra high density integrated circuit packages |
6171888, | Mar 08 1996 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Multi-layer tab tape having distinct signal, power and ground planes, semiconductor device assembly employing same, apparatus for and method of assembling same |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
May 09 2000 | Micron Technology, Inc. | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Feb 19 2002 | ASPN: Payor Number Assigned. |
May 12 2005 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
May 06 2009 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Jul 12 2013 | REM: Maintenance Fee Reminder Mailed. |
Dec 04 2013 | EXP: Patent Expired for Failure to Pay Maintenance Fees. |
Date | Maintenance Schedule |
Dec 04 2004 | 4 years fee payment window open |
Jun 04 2005 | 6 months grace period start (w surcharge) |
Dec 04 2005 | patent expiry (for year 4) |
Dec 04 2007 | 2 years to revive unintentionally abandoned end. (for year 4) |
Dec 04 2008 | 8 years fee payment window open |
Jun 04 2009 | 6 months grace period start (w surcharge) |
Dec 04 2009 | patent expiry (for year 8) |
Dec 04 2011 | 2 years to revive unintentionally abandoned end. (for year 8) |
Dec 04 2012 | 12 years fee payment window open |
Jun 04 2013 | 6 months grace period start (w surcharge) |
Dec 04 2013 | patent expiry (for year 12) |
Dec 04 2015 | 2 years to revive unintentionally abandoned end. (for year 12) |