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The ornamental design for a semiconductor device, as shown and described.
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FIG. 1 is a front, top and right side perspective view of a semiconductor device, showing my new design;
FIG. 2 is a front elevational view thereof;
FIG. 3 is a rear elevational view thereof;
FIG. 4 is a top plan view thereof;
FIG. 5 is a bottom plan view thereof;
FIG. 6 is a left side elevational view thereof; and,
FIG. 7 is a right side elevational view thereof.
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| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Sep 30 2002 | Kabushiki Kaisha Toshiba | (assignment on the face of the patent) | / | |||
| Nov 22 2002 | KOMOTO, SATOSHI | Kabushiki Kaisha Toshiba | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 013549 | /0149 |
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