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The ornamental design for a base for a semiconductor carrier, as shown and described.
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FIG. 1 is a front view of a base for a semiconductor carrier showing our new design, the rear view being a mirror image thereof;
FIG. 2 is a top view thereof;
FIG. 3 is a bottom view thereof, the perforations shown in dashed lines being no part of the claimed design;
FIG. 4 is a right-side view thereof;
FIG. 5 is a left-side view thereof; and,
FIG. 6 is a perspective view thereof.
Nakamura, Yuji, Suzuki, Katsumi, Ishibashi, Takahiro, Kobori, Eiji
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May 10 2005 | Yamaichi Electronics Co. | (assignment on the face of the patent) | / |
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