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The ornamental design for portion of a semiconductor device, as shown and described.
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FIG. 1 is a top plan view of portion of a semiconductor device, showing my new design; the opposite side being a mirror image thereof;
FIG. 2 is a front elevational view thereof;
FIG. 3 is a right side elevational view thereof; the opposite side being a mirror image thereof;
FIG. 4 is a rear elevational view thereof; and,
FIG. 5 is an enlarged fragmented rear elevational view thereof, taken along the line 5—5 in FIG. 2.
The broken lines are for illustrative purposes only and form no part of the claimed design.
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Oct 07 2004 | MIZUKOSHI, YUKIKO | Kabushiki Kaisha Toshiba | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 016029 | /0035 | |
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Mar 02 2018 | Kabushiki Kaisha Toshiba | TOSHIBA MEMORY CORPORATION | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 045175 | /0632 | |
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