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Patent
D473198
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Priority
Oct 26 2001
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Filed
Apr 26 2002
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Issued
Apr 15 2003
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Expiry
Apr 15 2017
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Assg.orig
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Entity
unknown
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5
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9
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n/a
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The ornamental design for a semiconductor device, as shown and described.
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FIG. 1 is a top plan view of a semiconductor device, showing our new design; a bottom plan view being a mirror image thereof;
FIG. 2 is a right side elevational view thereof; a left side elevational view being a mirror image thereof;
FIG. 3 is a front elevational view thereof; and,
FIG. 4 is a rear elevational view thereof.
Ozawa, Isao, Iijima, Toshitsune
Patent |
Priority |
Assignee |
Title |
4602271, |
Jul 22 1981 |
International Business Machines Corporation |
Personalizable masterslice substrate for semiconductor chips |
6300685, |
Aug 20 1998 |
OKI SEMICONDUCTOR CO , LTD |
Semiconductor package |
6307269, |
Jul 11 1997 |
LONGITUDE SEMICONDUCTOR S A R L |
Semiconductor device with chip size package |
D319045, |
Apr 13 1988 |
IBIDEN CO , LTD , A JAPANESE CORP |
Semi-conductor substrate with conducting pattern |
D319629, |
Apr 13 1988 |
IBIDEN CO , LTD , A JAPANESE CORP |
Semiconductor substrate with conducting pattern |
D319814, |
Apr 13 1988 |
IBIDEN CO , LTD |
Semi-conductor substrate with conducting pattern |
D442150, |
Jul 24 2000 |
|
RF module board of wireless telephone |
D457146, |
Nov 29 2000 |
Kabushiki Kaisha Kaisha Toshiba |
Substrate for a semiconductor element |
JP9003455, |
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Maintenance Fee Events |
n/a
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Maintenance Schedule |
n/a