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The ornamental design for a circuit board, as shown and described.
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FIG. 1 is a front perspective of the invention.
FIG. 2 is a plan elevation of the invention.
FIG. 3 is a bottom plan of the invention.
FIG. 4 is a front elevation of the invention.
FIG. 5 is a rear elevation of the invention.
FIG. 6 is a right end elevation of the invention; and,
FIG. 7 is a left end elevation of the invention.
The broken lines define the boundary of the claimed design and form no part of the claimed design.
Enderlein, Janos-Gerold, Romahn, Jörg
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| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| May 01 2003 | Siemens Aktiengesellschaft | (assignment on the face of the patent) | / | |||
| Aug 13 2003 | ENDERLEIN, JANOS-GEROLD | Siemens Aktiengesellschaft | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 014466 | /0660 | |
| Aug 13 2003 | ROMAHN, JORG | Siemens Aktiengesellschaft | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 014466 | /0660 |
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