Semiconductor integrated circuit designing method and system using a design rule modification

Abstract

A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

and, as shown in FIG. 3.

According to the present embodiment, as set out above, the values of the design rules can be calculated with the use of an actual device pattern and it is, therefore, possible to calculate an exact design rule, in a shorter period of time, compatible with processes actually in use. Further, since this is a design rule also taking into consideration the mask data processing assumed to be done with an actual device, it is possible to compromise between the mask data processing time and the chip size increase resulting from less strict design rule. By providing the reference evaluation value, a faster decision is made for OK (good) or NG (no good) and, in addition, a readier numerical evaluation is also made on the design rule. Further, by distinguishing between the design rule exerting an influence on the evaluation value and other design rules, it is easier to decide whether any given design rule should be set stricter or any given design rule should be set more lenient and, by doing so, it is possible to easily judge to which patterns specific attention should be paid during the work-processing and mask data processing.

It is to be noted that the design rules may be prepared not only using the compaction tool and simulator as set out above but also additionally preparing an actual mask and performing a transfer test, etc.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Claims

1. A method for designing a semiconductor integrated circuit, executed by a computer programmed to perform the method, the method comprising:

compacting a design layout of a semiconductor integrated circuit, using a computer, on the basis of a given design rule of the semiconductor integrated circuit to obtain a compacted pattern;

predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit, using a computer, on the basis of the compacted pattern;

obtaining an evaluated value, using a computer, by comparing the predicted pattern with the compacted pattern;

deciding, using a computer, whether the evaluated value satisfies a predetermined condition; and

modifying the design rule, using a computer, when the evaluated value is decided as not satisfying the predetermined condition.

2. A method according to claim 1, wherein the pattern to be formed at a surface area of a wafer is predicted, using a computer, using data obtained by converting data of the compacted pattern to mask data for photolithography or data for electron beam lithography.

3. A method according to claim 1, wherein the pattern to be formed at a surface area of a wafer is predicted, using a computer, using at least one model selected from a first prediction model, second prediction model and third prediction model, the first prediction model being a model for calculating a light exposed state of a resist on the wafer when the compacted pattern is projected on the resist, the second prediction model being a model for calculating a resist pattern configuration after the resist has been developed, and the third prediction model being a model for calculating a wafer surface configuration after the wafer has been work-processed using the resist pattern.

4. A system having a computer readable medium including instructions for designing a semiconductor integrated circuit, comprising:

means for compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule of the semiconductor integrated circuit to obtain a compacted pattern;

means for predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern;

means for obtaining an evaluated value by comparing the predicted pattern with the compacted pattern;

means for deciding whether the evaluated value satisfies a predetermined condition; and

means for modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.

5. A system according to claim 4, wherein the pattern to be formed at a surface area of a wafer is predicted using data obtained by converting data of the compacted pattern to mask data for lithography or data for electron beam lithography.

6. A system according to claim 4, wherein the pattern to be formed at a surface area of a wafer is predicted using at least one model selected from a first prediction model, second prediction model and third prediction model, the first prediction model being a model for calculating a light exposed state of a resist on the wafer when the compacted pattern is projected on the resist, the second prediction model being a model for calculating a resist pattern configuration after the resist has been developed, and the third prediction model being a model for calculating a wafer surface configuration after the wafer has been work-processed using the resist pattern.

7. A non-transitory computer readable storage medium configured to store encoded with a computer program product storing program instructions for causing a computer to compact a design layout of a semiconductor integrated circuit on the basis of a given design rule of the semiconductor integrated circuit to obtain a compacted pattern, causing the computer to predict a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, causing the computer to obtain an evaluated value by comparing the predicted pattern with the compacted pattern, causing the computer to decide whether the evaluated value satisfies a predetermined condition, and causing the computer to modify the design rule when the evaluated value is decided as not satisfying the predetermined condition the computer providing a modified design layout of a semiconductor integrated circuit based on the modified design rule.

8. A method for preparing a design rule for a semiconductor integrated circuit, executed by a computer programmed to perform the method, the method comprising:

obtaining a pattern of a design layout, using a computer, on the basis of a given design rule of the semiconductor integrated circuit;

predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit, using a computer, on the basis of the obtained pattern;

obtaining an evaluated value, using a computer, by comparing the predicted pattern with the obtained pattern;

deciding whether the evaluated value satisfies a predetermined condition, using a computer;

modifying the given design rule, using a computer, when the evaluated value is decided as not satisfying the predetermined condition; and

determining the given design rule as a fixed design rule for the semiconductor integrated circuit, using a computer, when the evaluated value is decided as satisfying the predetermined condition.

9. A method according to claim 8, wherein the pattern to be formed at a surface area of a wafer is predicted, using a computer, using data obtained by converting data of the obtained pattern to mask data for photolithography or data for electron beam lithography.

10. A method according to claim 8, wherein the pattern formed at a surface area of a wafer is predicted, using a computer, using at least one model selected from a first prediction model, a second prediction model and a third prediction model, the first prediction model being a model for calculating a light exposed state of a resist on the wafer when the obtained pattern is projected on the resist, the second prediction model being a model for calculating a resist pattern configuration after the resist has been developed, and the third prediction model being a model for calculating a wafer surface configuration after the wafer has been work-processed using the resist pattern configuration.

11. A layout used for producing a semiconductor integrated circuit, comprising a layout pattern designed using the design rule prepared by the method according to claim 8, instructions for executing the method being stored on a computer readable medium, wherein the layout is associated with the layout pattern produced using the prepared design rule.

12. A layout according to claim 11, wherein the layout pattern includes a standard cell pattern.

13. A layout according to claim 11, wherein the layout pattern includes a pattern for placement and routing.

14. A method for designing a layout for a semiconductor integrated circuit, executed by a computer programmed to perform the method, the method comprising:

obtaining a pattern of a design layout, using a computer, on the basis of a given design rule of the semiconductor integrated circuit;

predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit, using a computer, on the basis of the obtained pattern;

obtaining an evaluated value, using a computer, by comparing the predicted pattern with the obtained pattern;

deciding whether the evaluated value satisfies a predetermined condition, using a computer;

modifying the given design rule, using a computer, when the evaluated value is decided as not satisfying the predetermined condition;

determining the given design rule as a fixed design rule for the semiconductor integrated circuit, using a computer, when the evaluated value is decided as satisfying the predetermined condition; and

designing a layout pattern for the semiconductor integrated circuit, using a computer, using the fixed design rule.

15. A method according to claim 14, wherein the pattern to be formed at a surface area of a wafer is predicted, using a computer, using data obtained by converting data of the obtained pattern to mask data for photolithography or data for electron beam lithography.

16. A method according to claim 14, wherein the pattern to be formed at a surface area of a wafer is predicted, using a computer, using at least one model selected from a first prediction model, a second prediction model and a third prediction model, the first prediction model being a model for calculating a light exposed state of a resist on the wafer when the obtained pattern is projected on the resist, the second prediction model being a model for calculating a resist pattern configuration after the resist has been developed, and the third prediction model being a model for calculating a wafer surface configuration after the wafer has been work-processed using the resist pattern configuration.

17. A method according to claim 14, wherein the layout pattern includes a standard cell pattern.

18. A method according to claim 14, wherein the layout pattern includes a pattern for placement and routing.

19. A method for manufacturing a semiconductor device, comprising projecting a pattern corresponding to the layout designed by the method according to claim 14, onto a photoresist on a semiconductor substrate.

20. A method according to claim 1, wherein the given design rule defines a distance between patterns in different layers of the semiconductor integrated circuit.

21. A system according to claim 4, wherein the given design rule defines a distance between patterns in different layers of the semiconductor integrated circuit.

22. The non-transitory computer readable storage medium according to claim 7, wherein the given design rule defines a distance between patterns in different layers of the semiconductor integrated circuit.

23. A method according to claim 8, wherein the given design rule defines a distance between patterns in different layers of the semiconductor integrated circuit.

24. A layout according to claim 11, wherein the given design rule defines a distance between patterns in different layers of the semiconductor integrated circuit.

25. A method according to claim 14, wherein the given design rule defines a distance between patterns in different layers of the semiconductor integrated circuit.

26. A method according to claim 19, wherein the given design rule defines a distance between patterns in different layers of the semiconductor integrated circuit.

27. A method for manufacturing a semiconductor device, comprising:

forming a circuit pattern on a semiconductor wafer based on the layout designed by the method according to claim 14.

28. A computer program product configured to store program instructions for causing a computer to perform the method according to claim 14.