Data security method and device for computer modules

Abstract

A security method for an attached computer module in a computer system. The security method reads a security identification number in an attached computer module and compares it to a security identification number in a console, which houses the attached computer module. Based upon a relationship between these numbers, a security status is selected. The security status determines the security level of operating the computer system.

Description

FIG. 9 depicts a peripheral console configuration.

temper

The reserved data packet types can be used to support non-PCI bus transactions, e.g., USB transactions. The bits sent in the first nibble of each data packet indicate the type of the data packet. FIG. 24 is a table showing different types of first nibbles and their corresponding data packet types.

Although the functionality above has been generally described in terms of a specific sequence of steps, other steps can also be used. Here, the steps can be implemented in a combination of hardware, firmware, and software. Either of these can be further combined or even separated. Depending upon the embodiment, the functionality can be implemented in a number of different ways without departing from the spirit and scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives.

While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.

Claims

1. A security protection method for a computer module, said method comprising:

inserting the computer module into a console;

initiating a security program in said module to read a security identification of said console and to read a security identification of said computer module;

determining of a predetermined security status based upon a relationship of said console identification and said computer module identification;

selecting said predetermined security status; and

operating said computer module based upon said security status.

2. The method of claim 1 wherein said predetermined security status disables a network access to the computer module.

3. The method of claim 1 wherein said predetermined security status disables a secondary storage of information from said computer module to substantially prevent information to be transferred from a memory of the computer module to said secondary storage.

4. The method of claim 1 wherein said security program is provided in a system BIOS.

5. The method of claim 1 wherein said step of initiating reads said security identification of said computer module from a flash memory device.

6. The method of claim 1 wherein said step of initiating reads said security identification of said console from a flash memory device.

7. The method of claim 1 wherein said console is selected from a desktop home computing device, an office desktop computing device, a mobile computing device, a television sot-top computing device, and a co-worker's computing device.

8. A system for secured information transactions, the system comprising:

a console comprising a peripheral controller housed in the console;

a user identification input device coupled to the peripheral controller, the user identification input device being provided for user identification data; and

an attached computer module coupled to the console, the attached computer module comprising a security memory device stored with the user identification data.

9. The system of claim 8 wherein the user identification input device is a finger print reader.

10. The system of claim 8 wherein the user identification input device is a voice processing device.

11. A method for operating a module computer into one of a plurality of network systems, the method comprising:

providing a computer module, the module comprising a connection program;

inserting the computer module into a computer console, the computer console having access to a network;

receiving connection information from the computer console;

configuring the connection program to adapt to the connection information; and

establish a connection between the computer module and a server coupled to the network.

12. The method of claim 11 wherein the connection information comprises a connection protocol for providing the connection.

13. The method of claim 12 wherein the connection protocol is selected from TCP/IP, or mobile IP.

14. A method of increasing external peripheral data communication speed of a computer, comprising:

connecting a central processing unit (CPU) directly to a peripheral bridge on a printed circuit board of a computer;

connecting a first low voltage differential signal (lvds) channel directly to the peripheral bridge on the printed circuit board, the first lvds channel comprising two unidirectional, serial channels that transmit data in opposite directions;

providing a connector for the computer for connection to a console;

providing a second lvds channel to couple to the console through the connector, the second lvds channel comprising two unidirectional, serial channels that transmit data in opposite directions;

conveying encoded address and data bits of a peripheral component Interconnect (PCI) bus transaction in serial form over the first lvds channel and the second lvds channel to preserve the PCI bus transaction; and

enabling the PCI bus transaction to be conveyed serially through the second lvds channel to the console to improve peripheral data communication speed between the computer and the console.

15. The method of claim 14 further comprising attaching system memory directly to the CPU.

16. The method of claim 14 further comprising:

coupling a graphics controller to the CPU; and

enabling the transmission of digital video signals from the graphics controller through the connector to an external display.

17. A method of increasing external peripheral data communication speed of a computer, comprising:

providing an integrated central processing unit (CPU) and graphics controller in a single chip, on a printed circuit board of a computer;

providing digital video signals directly from the integrated CPU and graphics controller;

connecting a first low voltage differential signal (lvds) channel directly to the peripheral bridge on the printed circuit board, the first lvds channel comprising two unidirectional, serial channels that transmit data in opposite directions;

providing a connector for the computer for connection to a console;

providing a second lvds channel to couple to the console through the connector, the second lvds channel comprising two unidirectional, serial channels that transmit data in opposite directions;

enabling encoded address and data bits of a peripheral component Interconnect (PCI) bus transaction to be conveyed in serial form over the second lvds channel to preserve the PCI bus transaction; and

enabling the PCI bus transaction to be conveyed serially through the second lvds channel to the console to improve peripheral data communication speed between the computer and the console.

18. The method of claim 17 further comprising attaching system memory directly to the CPU.

19. The method of claim 17 further comprising enabling the transmission of the digital video signals from the integrated CPU and graphics controller through the connector to an external display.

20. A method of increasing external data communication speed of a computer, comprising:

providing an integrated central processing unit (CPU) and graphics controller on a printed circuit board of a computer;

connecting a first low voltage differential signal (lvds) channel directly to said integrated CPU and graphics controller, the first lvds channel comprising two unidirectional, serial channels that transmit data in opposite directions;

providing a connector for the computer that connects to a console;

providing a second lvds channel to couple to the console through the connector, the second lvds channel comprising two unidirectional, serial channels that transmit data in opposite directions; and

enabling Universal serial bus (USB) protocol data to be conveyed over the second lvds channel.

21. The method of claim 20 further comprising conveying encoded address and data bits of a peripheral component Interconnect (PCI) bus transaction for peripheral data communication in serial form over the first lvds channel.

22. The method of claim 20 further comprising conveying said USB protocol data through the second lvds channel upon coupling to the console in a plug and play operation.

23. A method of increasing external data communication speed of a computer, comprising:

connecting a central processing unit (CPU) directly to a peripheral bridge on a printed circuit board of a computer;

connecting a first low voltage differential signal (lvds) channel directly to the peripheral bridge, the first lvds channel comprising two unidirectional, serial channels that transmit data in opposite directions;

providing a connector for the computer that connects to a console;

providing a second lvds channel to couple to the console through the connector, the second lvds channel comprising two unidirectional, serial channels that transmit data in opposite directions; and

enabling Universal serial bus (USB) protocol data to be conveyed over the second lvds channel.

24. The method of claim 23 further comprising conveying encoded address and data bits of a peripheral component Interconnect (PCI) bus transaction for peripheral data communication in serial form over the first lvds channel.

25. The method of claim 23 further comprising conveying the USB protocol data through the second lvds channel upon coupling to the console in a plug and play operation.

26. A method to improve computer data transaction performance, comprising:

connecting a central processing unit (CPU) directly to a peripheral bridge, without any intervening peripheral component Interconnect (PCI) bus, on a printed circuit board in a computer;

connecting a low voltage differential signal (lvds) channel directly to the peripheral bridge on the printed circuit board, the lvds channel comprising two unidirectional, serial channels that transmit data in opposite directions;

increasing data throughput of the serial channels by providing each channel with multiple pairs of differential signal lines to improve peripheral data performance of the computer;

conveying encoded address and data bits of a PCI bus transaction in serial form over the lvds channel to preserve the PCI bus transaction;

connecting system memory directly to the CPU; and

coupling a mass storage device to the peripheral bridge.

27. The method of claim 26 further comprising using flash memory as a mass storage device.

28. The method of claim 26 further comprising coupling the lvds channel to an ethernet device to increase data communication speed between the CPU and an external ethernet network.

29. A method of increasing system data transaction performance, comprising:

connecting a central processing unit (CPU) directly to a peripheral bridge, without any intervening peripheral component Interconnect (PCI) bus, on a printed circuit board;

connecting a low voltage differential signal (lvds) channel directly to the peripheral bridge on the printed circuit board, the first lvds channel comprising two unidirectional, serial channels that transmit data in opposite directions;

increasing data throughput of the serial channels by providing each channel with multiple pairs of differential signal lines;

conveying encoded address and data bits of a PCI bus transaction in serial form over the lvds channel to preserve a PCI bus transaction;

coupling a mass storage device to the peripheral bridge;

coupling the lvds channel to an ethernet device;

connecting the computer to an ethernet network; and

enabling data communication between the CPU and the ethernet network through the lvds channel.

30. The method of claim 29 further comprising attaching system memory directly to the CPU.

31. The method of claim 29 further comprising using flash memory as a mass storage device.

32. A method of increasing system data transaction performance, comprising:

connecting a central processing unit (CPU) directly to a peripheral bridge, without any intervening peripheral component Interconnect (PCI) bus, on a printed circuit board;

mounting the printed circuit board in a computer module;

connecting a first low voltage differential signal (lvds) channel directly to the peripheral bridge on the printed circuit board, the first lvds channel comprising two unidirectional, serial channels that transmit data in opposite directions;

increasing data throughput of the serial channels by providing each channel with multiple pairs of differential signal lines;

conveying encoded address and data bits of a PCI bus transaction in serial form over the first lvds channel to preserve a PCI bus transaction;

coupling the first lvds channel to an ethernet device on the printed circuit board;

inserting the computer module into a console;

connecting the computer module to an ethernet network through the ethernet device;

connecting power to the computer module; and

enabling data communication between the CPU and the ethernet network through the first lvds channel.

33. The method of claim 32 further comprising providing a power connection in the console to supply power to the computer module.

34. The method of claim 32 further comprising:

connecting a second low voltage differential signal (lvds) channel directly to the peripheral bridge; and

coupling a hard disk drive to the second lvds channel.

35. A method to improve computer storage data access performance, comprising:

connecting a central processing unit (CPU) directly to a peripheral bridge, without any intervening peripheral component Interconnect (PCI) bus, on a printed circuit board in a computer;

connecting a low voltage differential signal (lvds) channel directly to the peripheral bridge on the printed circuit board, the lvds channel comprising two unidirectional, serial channels that transmit data in opposite directions;

increasing data throughput of the serial channels by providing each channel with multiple pairs of differential signal lines;

conveying encoded address and data bits of a PCI bus transaction in serial form over the lvds channel to preserve the PCI bus transaction;

connecting system memory directly to the CPU to improve memory data performance of the computer; and

coupling a mass storage device to the peripheral bridge through the lvds channel.

36. The method of claim 35 further comprises using flash memory as mass storage device.