A security method for an attached computer module in a computer system. The security method reads a security identification number in an attached computer module and compares it to a security identification number in a console, which houses the attached computer module. Based upon a relationship between these numbers, a security status is selected. The security status determines the security level of operating the computer system.

Patent
   RE42984
Priority
May 14 1999
Filed
Sep 16 2009
Issued
Nov 29 2011
Expiry
May 14 2019
Assg.orig
Entity
Large
17
224
EXPIRED
0. 37. (Twice Amended) A method to connect a computer module to a network, the method comprising:
providing a computer module, the computer module comprising (a) a central processing unit and (b) a storage device comprising a connection program;
inserting the computer module into a computer console in a “plug and play” operation, the computer console comprising (a) a low voltage differential signal channel comprising two sets of unidirectional, multiple serial bit channels to communicate an encoded serial bit stream of peripheral component Interconnect (“PCI”) bus transaction in opposite directions and (b) a networking device to provide access to an external network;
receiving connection information from the computer console to the computer module; and
using the connection program, establishing a connection between the computer module and the external network.
0. 52. A computer system comprising:
a console comprising a power supply; and
a computer module coupled to the console, the computer module comprising
a central processing unit to operate on a varying clock frequency to vary a power consumption of the central processing unit while in operation,
a low voltage differential signal channel comprising two sets of unidirectional, multiple serial bit channels to transmit data in opposite directions,
a peripheral bridge comprising an interface controller coupled to the low voltage differential signal channel to communicate an encoded serial bit stream of peripheral component Interconnect (“PCI”) bus transaction, the interface controller coupled to the central processing unit without any intervening PCI bus, and
a graphics controller coupled to the central processing unit,
wherein the computer module is configured to receive power from the power supply.
0. 58. An information system comprising:
a console comprising
a power supply and
a first low voltage differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions; and
a computer module coupled to the console, the computer module comprising
a central processing unit comprising an integrated interface controller,
a mass storage device coupled to the central processing unit,
a graphics controller coupled to the central processing unit, and
a second low voltage differential signal channel extending directly from the central processing unit, the second low voltage differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions,
wherein the interface controller is coupled to the console through the second low voltage differential signal channel,
wherein the computer module is configured to receive power from the power supply.
0. 20. A system for information transaction, the system comprising:
a console comprising
a power supply,
a first low voltage differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions, and
a removable media drive housed in the console; and
a computer module coupled to the console, the computer module comprising
a central processing unit comprising an interface controller,
a mass storage device coupled to the central processing unit, and
a second low voltage differential signal channel extending directly from the interface controller, the second low voltage differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions, and
wherein the interface controller is coupled to the console through the second low voltage differential signal channel,
wherein the computer module is configured to receive power from the power supply.
0. 48. A computer system comprising:
a console comprising a power supply; and
a computer module coupled to the console, the computer module comprising
a central processing unit,
a low voltage differential signal channel comprising two sets of unidirectional, multiple serial bit channels to transmit data in opposite directions,
an integrated interface controller and bridge unit coupled to the low voltage differential signal channel to communicate an encoded serial bit stream of address and data of peripheral component Interconnect (“PCI”) bus transaction, the integrated interface controller and bridge unit directly coupled to the central processing unit without any intervening PCI bus, and
a mass storage device coupled to the central processing unit,
wherein the computer module is configured to receive power from the power supply, and the computer module is configured to communicate, through ethernet, to a local area network upon coupling of the computer module to the console.
0. 27. An information transaction system comprising:
a console comprising
an integrated keyboard,
an integrated liquid crystal display,
a first low voltage differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions, and
an interface controller coupled to the first low voltage differential signal channel to communicate an encoded serial bit stream of peripheral component Interconnect (“PCI”) bus transaction; and
a computer module coupled to the console in a “plug and play” operation, the computer module comprising
a central processing unit,
a peripheral bridge coupled to the central processing unit without any intervening PCI bus,
a second low voltage differential signal channel coupled to the peripheral bridge, the second low voltage differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions, and
a mass storage device comprising a flash memory.
0. 44. A system to connect a computer module to a network, the system comprising:
a console comprising
a power supply and
a connection to a network; and
a computer module coupled to the console in a “plug and play” operation, the computer module comprising
a processing unit,
a low voltage differential signal channel comprising two sets of unidirectional, multiple serial bit channels to transmit data in opposite directions,
a peripheral bridge comprising an interface controller coupled to the low voltage differential signal channel to communicate an encoded serial bit stream of address and data of peripheral component Interconnect (“PCI”) bus transaction, the peripheral bridge coupled to the processing unit without any intervening PCI bus, and
a mass storage device comprising a connection program,
wherein the computer module is configured to receive power from the power supply, and the connection program is configured to establish communication with the network through the console.
0. 55. A computer system for secured information transaction, the computer system comprising:
a console to connect to a network;
a keyboard coupled to the console; and
a computer module coupled to the console, the computer module comprising
a central processing unit,
a low voltage differential signal channel comprising two sets of unidirectional, multiple serial bit channels to transmit data in opposite directions,
a peripheral bridge comprising an interface controller coupled to the low voltage differential signal channel to communicate an encoded serial bit stream of peripheral component Interconnect (“PCI”) bus transaction, the interface controller coupled to the central processing unit without any intervening PCI bus, and
a mass storage unit storing a security program and a first user identification data,
wherein the security program is configured to receive a second user identification data via the keyboard, perform a comparison of the first user identification data and the second user identification data, and permit access to the computer module based on the comparison.
0. 34. An information transaction system comprising:
a console comprising
a power supply,
a first low voltage differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions, and
a removable media drive housed in the console; and
a computer module coupled to the console, the computer module comprising
an integrated interface controller and central processing unit configured as a single chip,
a flash memory comprising a security identification to provide access protection for the computer module, and
a second low voltage differential signal channel extending directly from the integrated interface controller and central processing unit, the second low voltage differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions,
wherein the integrated interface controller and central processing unit is coupled to the console through the second low voltage differential signal channel,
wherein the computer module is configured to receive power from the power supply.
0. 24. A system to connect a computer module to a network, the system comprising:
a console comprising
a power supply,
a first low voltage differential signal channel comprising two sets of unidirectional, multiple serial bit channels to communicate an encoded serial bit stream of peripheral component Interconnect (“PCI”) bus transaction in opposite directions, and
an ethernet controller to provide access to a network; and
a computer module coupled to the console and powered by the power supply, the computer module comprising
a central processing unit comprising an integrated interface controller,
a second low voltage differential signal channel directly coupled to the integrated interface controller, the second low voltage differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions,
a mass storage device coupled to the central processing unit, and
a connection software code,
wherein, upon coupling to the console, the computer module is configured to establish a connection to the network using the connection software code.
0. 40. A computer system comprising:
a console comprising
a power supply and
a first low voltage differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions; and
a computer module coupled to the console, the computer module comprising
a central processing unit to operate on a varying clock frequency to vary a power consumption of the central processing unit while in operation,
a mass storage unit coupled to the central processing unit,
a second low voltage differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions, and
a peripheral bridge directly coupled to the central processing unit without any intervening peripheral component Interconnect bus, the peripheral bridge comprising an interface controller to output a serial bit stream that is conveyed over the second low voltage differential signal channel,
wherein the interface controller is coupled to the console through the second low voltage differential signal channel,
wherein the computer module is configured to receive power from the power supply.
0. 17. A system for information transaction, the system comprising:
a console comprising
an integrated liquid crystal display and
a first low voltage differential signal channel comprising two sets of unidirectional, multiple serial bit channels to communicate an encoded serial bit stream of peripheral component Interconnect (“PCI”) bus transaction in opposite directions; and
a computer module coupled to the console in a “plug and play” operation, the computer module comprising
a central processing unit,
a peripheral bridge directly coupled to the central processing unit without any intervening PCI bus, the peripheral bridge comprising an interface controller that is integrated with the peripheral bridge,
a second differential signal channel extending directly from the interface controller, the second differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions,
a mass storage device coupled to the central processing unit, and
wherein the interface controller is configured to communicate a differential signaling serial bit stream with the console through the second differential signal channel.
0. 31. A system for information transaction, the system comprising:
a console comprising
an integrated keyboard,
an integrated liquid crystal display, and
a first low voltage differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions; and
a computer module coupled to the console, the computer module comprising
a central processing unit,
a peripheral bridge directly coupled to the central processing unit without any intervening peripheral component Interconnect bus, the peripheral bridge comprising an interface controller,
a mass storage device comprising a flash memory, and
a second low voltage differential signal channel extending directly from the interface controller, the second low voltage differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions,
wherein the interface controller is coupled to the console through the second low voltage differential signal channel,
wherein the first low voltage differential signal channel is coupled to the second low voltage differential signal channel upon coupling of the computer module to the console.
0. 14. A system for information transaction, the system comprising:
a console comprising
a first low voltage differential signal channel comprising two sets of unidirectional, multiple serial bit channels to transmit data in opposite directions,
a first interface controller coupled to the first low voltage differential signal channel to communicate an encoded serial bit stream of peripheral component Interconnect (“PCI”) bus transaction,
a power supply, and
a hard disk drive housed in the console; and
a computer module coupled to the console, the computer module comprising
a central processing unit,
a peripheral bridge directly coupled to the central processing unit without any intervening PCI bus, the peripheral bridge comprising a second interface controller,
a second differential signal channel extending directly from the second interface controller, the second differential signal channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions,
a mass storage device coupled to the central processing unit through the peripheral bridge, and
a security mechanism to provide access protection for the computer module,
wherein the computer module is configured to receive power from the power supply.
0. 1. A security protection method for a computer module, said method comprising:
inserting the computer module into a console;
initiating a security program in said module to read a security identification of said console and to read a security identification of said computer module;
determining of a predetermined security status based upon a relationship of said console identification and said computer module identification;
selecting said predetermined security status; and
operating said computer module based upon said security status.
0. 2. The method of claim 1 wherein said predetermined security status disables a network access to the computer module.
0. 3. The method of claim 1 wherein said predetermined security status disables a secondary storage of information from said computer module to substantially prevent information to be transferred from a memory of the computer module to said secondary storage.
0. 4. The method of claim 1 wherein said security program is provided in a system BIOS.
0. 5. The method of claim 1 wherein said step of initiating reads said security identification of said computer module from a flash memory device.
0. 6. The method of claim 1 wherein said step of initiating reads said security identification of said console from a flash memory device.
0. 7. The method of claim 1 wherein said console is selected from a desktop home computing device, an office desktop computing device, a mobile computing device, a television sot-top computing device, and a co-worker's computing device.
0. 8. A system for secured information transactions, the system comprising:
a console comprising a peripheral controller housed in the console;
a user identification input device coupled to the peripheral controller, the user identification input device being provided for user identification data; and
an attached computer module coupled to the console, the attached computer module comprising a security memory device stored with the user identification data.
0. 9. The system of claim 8 wherein the user identification input device is a finger print reader.
0. 10. The system of claim 8 wherein the user identification input device is a voice processing device.
0. 11. A method for operating a module computer into one of a plurality of network systems, the method comprising:
providing a computer module, the module comprising a connection program;
inserting the computer module into a computer console, the computer console having access to a network;
receiving connection information from the computer console;
configuring the connection program to adapt to the connection information; and
establish a connection between the computer module and a server coupled to the network.
0. 12. The method of claim 11 wherein the connection information comprises a connection protocol for providing the connection.
0. 13. The method of claim 12 wherein the connection protocol is selected from TCP/IP, or mobile IP.
0. 15. The system of claim 14, wherein the computer module further comprises a computing environment for a user.
0. 16. The system of claim 14, wherein the computer module is coupled to the console through serial bit stream data paths employing low voltage differential signaling.
0. 18. The system of claim 17, wherein the computer module further comprises a computing environment for a user.
0. 19. The system of claim 17, wherein the computer module further comprises a hardware dependent security code to perform security identification matching.
0. 21. The system of claim 20, wherein the first low voltage differential signal channel and the second low voltage differential signal channel are configured to transmit data in 10-bit packets.
0. 22. The system of claim 20, wherein the computer module further comprises a computing environment for a user.
0. 23. The system of claim 20, wherein the first low voltage differential signal channel is coupled to the second low voltage differential signal channel upon coupling of the computer module to the console.
0. 25. The system of claim 24, wherein the computer module is coupled to the console in a “plug and play” operation.
0. 26. The system of claim 24, wherein the computer module further comprises a computing environment for a user.
0. 28. The system of claim 27, wherein the central processing unit comprises an integrated circuit chip to operate on a varying clock frequency to vary a power consumption of the integrated circuit chip while in operation.
0. 29. The system of claim 27, wherein the computer module further comprises a computing environment for a user.
0. 30. The system of claim 27, wherein the peripheral bridge is directly coupled to the second low voltage differential signal channel to communicate a serial bit stream to the console.
0. 32. The system of claim 31, wherein the computer module further comprises a security program to specify a security identification.
0. 33. The system of claim 31, wherein the computer module further comprises a computing environment for a user.
0. 35. The system of claim 34, wherein the computer module further comprises a computing environment for a user.
0. 36. The system of claim 34, wherein the first low voltage differential signal channel is coupled to the second low voltage differential signal channel upon coupling of the computer module to the console.
0. 38. The method of claim 37, further comprising coupling the computer module to the low voltage differential signal channel.
0. 39. The method of claim 37, wherein establishing the connection between the computer module and the external network comprises communicating with the external network through ethernet.
0. 41. The computer system of claim 40, wherein the computer module further comprises a computing environment for a user.
0. 42. The computer system of claim 40, wherein the first low voltage differential signal channel is coupled to the second low voltage differential signal channel upon coupling of the computer module to the console for data communication.
0. 43. The computer system of claim 40, wherein the computer module is configured for insertion into the console as a “plug and play” operation.
0. 45. The system of claim 44, wherein the processing unit comprises an integrated circuit chip to operate on a varying clock frequency to vary a power consumption of the integrated circuit chip while in operation.
0. 46. The system of claim 44, wherein the connection to the network comprises an ethernet connection.
0. 47. The system of claim 44, wherein the computer module further comprises a computing environment for a user.
0. 49. The computer system of claim 48, wherein the computer module is configured for insertion into the console as a “plug and play” operation.
0. 50. The computer system of claim 48, wherein the mass storage device is a first mass storage device, and the console further comprises a second mass storage device coupled to the computer module and configured to receive power from the power supply.
0. 51. The computer system of claim 48, wherein the central processing unit is configured to operate on a varying clock frequency to vary a power consumption of the central processing unit while in operation.
0. 53. The computer system of claim 52, wherein the computer module further comprises a core computing environment for a user.
0. 54. The computer system of claim 52, wherein the computer module is configured for insertion into the console as a “plug and play” operation.
0. 56. The computer system of claim 55, wherein the security program is further configured to identify a predetermined security status and control a level of access privilege to the computer module.
0. 57. The computer system of claim 55, wherein the central processing unit is configured to operate on a varying clock frequency to vary a power consumption of the central processing unit while in operation.
0. 59. The information system of claim 58, wherein the first low voltage differential signal channel is coupled to the second low voltage differential signal channel for data communication upon coupling of the computer module to the console.
0. 60. The information system of claim 58, wherein the computer module is configured for insertion into the console as a “plug and play” operation.
0. 61. The system of claim 14, wherein the encoded serial bit stream comprises 10 bit packets.
0. 62. The system of claim 61, wherein the first interface controller is configured to output encoded PCI address and data bits in serial form that are conveyed over the first low voltage differential signal channel.
0. 63. The system of claim 14, wherein the second interface controller is integrated with the peripheral bridge as a single integrated unit.
0. 64. The system of claim 17, wherein the encoded serial bit stream of PCI bus transaction comprises information to permit decoding to create a PCI bus transaction across the first low voltage differential signal channel.
0. 65. The system of claim 17, wherein the mass storage device is coupled to the central processing unit through the peripheral bridge.
0. 66. The system of claim 20, wherein the central processing unit and the interface controller are integrated in a single chip.
0. 67. The system of claim 66, wherein the central processing unit comprises a graphics subsystem integrated in the single chip.
0. 68. The system of claim 24, wherein the encoded serial bit stream comprises encoded PCI address and data bits in serial form that are conveyed over the first low voltage differential signal channel as 10 bit packets.
0. 69. The system of claim 24, wherein the integrated interface controller is configured to output a serial bit stream that is conveyed over the second low voltage differential signal channel as data packets.
0. 70. The system of claim 69, wherein the serial bit stream comprises information of Universal Serial Bus protocol.
0. 71. The system of claim 30, wherein the peripheral bridge is configured to output the serial bit stream that is conveyed over the second low voltage differential signal channel as data packets.
0. 72. The system of claim 71, wherein the serial bit stream comprises information of Universal Serial Bus protocol.
0. 73. The system of claim 31, wherein the interface controller is integrated with the peripheral bridge as a single integrated unit.
0. 74. The system of claim 73, wherein the interface controller is configured to output a serial bit stream that is conveyed over the second low voltage differential signal channel as 10 bit packets.
0. 75. The system of claim 34, wherein the integrated interface controller and central processing unit comprises a graphics subsystem integrated in the single chip.
0. 76. The system of claim 34, wherein the integrated interface controller and central processing unit is configured to output a serial bit stream that is conveyed over the second low voltage differential signal channel as data packets.
0. 77. The system of claim 76, wherein the serial bit stream comprises information of Universal Serial Bus protocol.
0. 78. The method of claim 37, further comprising conveying, over the low voltage differential signal channel, the encoded serial bit stream as 10 bit packets.
0. 79. The method of claim 78, wherein conveying the encoded serial bit stream comprises conveying information to permit decoding to create a PCI bus transaction across the low voltage differential signal channel.
0. 80. The computer system of claim 40, wherein the interface controller is integrated with the peripheral bridge as a single integrated unit.
0. 81. The computer system of claim 80, wherein the serial bit stream is conveyed over the second low voltage differential signal channel as 10 bit packets.
0. 82. The computer system of claim 80, wherein the serial bit stream comprises information of Universal Serial Bus protocol.
0. 83. The system of claim 44, wherein the encoded serial bit stream comprises 10 bit packets.
0. 84. The system of claim 83, wherein the interface controller is configured to output the encoded serial bit stream that is conveyed over the low voltage differential signal channel.
0. 85. The computer system of claim 48, wherein the integrated interface controller and bridge unit is configured as a single integrated unit.
0. 86. The computer system of claim 85, wherein the integrated interface controller and bridge unit is configured to output the encoded serial bit stream as 10 bit packets that are conveyed over the low voltage differential signal channel.
0. 87. The computer system of claim 52, wherein the peripheral bridge is directly coupled to the central processing unit without any intervening PCI bus.
0. 88. The computer system of claim 87, wherein the interface controller is configured to output the encoded serial bit stream as 10 bit packets that are conveyed over the low voltage differential signal channel.
0. 89. The computer system of claim 88, wherein the encoded serial bit stream comprises information to permit decoding to create a PCI bus transaction across the low voltage differential signal channel.
0. 90. The computer system of claim 55, wherein the peripheral bridge is directly coupled to the central processing unit without any intervening PCI bus.
0. 91. The computer system of claim 90, wherein the interface controller is integrated with the peripheral bridge as a single integrated unit.
0. 92. The computer system of claim 91, wherein the encoded serial bit stream comprises encoded PCI address and data bits in serial form.
0. 93. The information system of claim 58, wherein the integrated interface controller is configured to output a serial bit stream that is conveyed over the second low voltage differential signal channel.
0. 94. The information system of claim 93, wherein the serial bit stream is conveyed over the second low voltage differential signal channel as 10 bit packets.
0. 95. The information system of claim 93, wherein the serial bit stream comprises information of Universal Serial Bus protocol.

FIG. 9 depicts a peripheral console configuration.temper

FIG. 16 is a schematic diagram of lines PCK, PD0 to PD3, and PCN. These lines are unidirectional LVDS lines for transmitting clock signals and bits from the HIC to the PIC. The bits on the PD0 to PD3 and the PCN lines are sent synchronously within every clock cycle of the PCK. Another set of lines, namely PCKR, PDR0 to PDR3, and PCNR, are used to transmit clock signals and bits from the PIC to HIC. The lines used for transmitting information from the PIC to the HIC have the same structure as those shown in FIG. 16, except that they transmit data in a direction opposite to that in which the lines shown in FIG. 16 transmit data. In other words they transmit information from the PIC to the HIC. The bits on the PDR0 to PDR3 and the PCNR lines are sent synchronously within every clock cycle of the PCKR. Some of the examples of control information that may be sent in the reverse direction, i.e., on PCNR line, include a request to switch data bus direction because of a pending operation (such as read data available), a control signal change in the target requiring communication in the reverse direction, target busy, and transmission error detected.

The XPBus which includes lines PCK, PD0 to PD3, PCN, PCKR, PDR0 to PDR3, and PCNR, has two sets of unidirectional lines transmitting clock signals and bits in opposite directions. The first set of unidirectional lines includes PCK, PD0 to PD3, and PCN. The second set of unidirectional lines includes PCKR, PDR0 to PDR3, and PCNR. Each of these unidirectional set of lines is a point-to-point bus with a fixed transmitter and receiver, or in other words a fixed master and slave bus. For the first set of unidirectional lines, the HIC is a fixed transmitter/master whereas the PIC is a fixed receiver/slave. For the second set of unidirectional lines, the PIC is a fixed transmitter/master whereas the HIC is a fixed receiver/slave. The LVDS lines of XPBus, a cable friendly and remote system I/O bus, transmit fixed length data packets within a clock cycle.

The XPBus lines, PD0 to PD3, PCN, PDR0 to PDR3 and PCNR, and the video data and clock lines, VPD and VPCK, are not limited to being LVDS lines, as they may be other forms of bit based lines. For example, in another embodiment, the XPBus lines may be IEEE 1394 lines.

It is to be noted that although each of the lines PCK, PD0 to PD3, PCN, PCKR, PDR0 to PDR3, PCNR, VPCK, and VPD is referred to as a line, in the singular rather than plural, each such line may contain more than one physical line. For example, in the embodiment shown in FIG. 16, each of lines PCK, PD0 to PD3 and PCN includes two physical lines between each driver and its corresponding receiver. The term line, when not directly preceded by the terms physical or conductive, is herein used interchangeably with a signal or bit channel of one or more physical lines for transmitting a signal. In the case of non-differential signal lines, generally only one physical line is used to transmit one signal. However, in the case of differential signal lines, a pair of physical lines is used to transmit one signal. For example, a pair of physical lines together transmit a signal in a bit line or bit channel in an LVDS or IEEE 1394 interface.

A bit based line (i.e., a bit line) is a line for transmitting serial bits. Bit based lines typically transmit bit packets and use a serial data packet protocol. Examples of bit lines include an LVDS line, an IEEE 1394 line, and a Universal Serial Bus (USB) line.

In the embodiment shown in FIG. 13, HIC 1319 is coupled to an integrated unit 1321 that includes a CPU, a cache and a north bridge. In another embodiment, such as that shown in FIG. 17, the CPU 1705 and north bridge 1710 are separate rather than integrated units. In yet another embodiment, such as that shown in FIG. 18, the HIC and PIC are integrated with the north and south bridges, respectively, such that integrated HIC and north bridge unit 1805 includes an HIC and a north bridge, while integrated PIC and south bridge unit 1810 includes a PIC and a south bridge. FIG. 19 shows an attached computer module with integrated CPU/NB/Graphics 1915 and Integrated HIC/SB 1920. FIG. 20 shows an attached computer module with single chip 2025 fully integrated: CPU, Cache, Core Logic, Graphics controller and Interface controller.

Although the functionality above has been generally described in terms of a specific sequence of steps, other steps can also be used. Here, the steps can be implemented in a combination of hardware, firmware, and software. Either of these can be further combined or even separated. Depending upon the embodiment, the functionality can be implemented in a number of different ways without departing from the spirit and scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives.

While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.

Chu, William W. Y.

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Sep 16 2009ACQis Technology, Inc.(assignment on the face of the patent)
Nov 01 2011ACQIS TECHNOLOGY, INC ACQIS LLCASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0271540398 pdf
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