Password protected modular computer method and device

Abstract

A method and device for securing a removable attached computer module (“ACM”) 10. ACM 10 inserts into a computer module Bay (“CMB”) 40 within a peripheral console to form a functional computer such as a desktop computer or portable computer. The present ACM 10 includes a locking system, which includes hardware and software 600, 700, to prevent accidental removal or theft of the ACM from the peripheral console. While ACM is in transit, further security is necessary against illegal or unauthorized use. If ACM contains confidential data, a high security method is needed to safeguard against theft.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

FIG. 8 is a block diagram of one embodiment of a computer system using the interface of the present invention.542

As suggested above, there are also differences between HIC 900 and PIC 1000. Some of the differences between HIC 900 and PIC 1000 include the following. First, receiver 1040 in PIC 1000, unlike receiver 940 in HIC 900, does not contain a synchronization unit. As mentioned above, the synchronization unit in HIC 900 synchronizes the PCKR clock to the PCK clock locally generated by PLL 950. PIC 1000 does not locally generate a PCK clock and, therefore, it does not have a locally generated PCK clock with which to synchronize the PCK clock signal that it receives from HIC 900. Another difference between PIC 1000 and HIC 900 is the fact that PIC 1000 contains a video parallel to serial converter 1089 whereas HIC 900 contains a video serial to parallel converter 980. Video parallel to serial converter 1089 receives 16 bit parallel video capture data and video control signals on the Video Port Data [0::15] and Video Port Control lines, respectively, from the video capture circuit (not shown in FIG. 10) and converts them to a serial video data stream that is transmitted on the VPD line to the HIC. The video capture circuit may be any type of video capture circuit that outputs a 16 bit parallel video capture data and video control signals. Another difference lies in the fact that PIC 1000, unlike HIC 900, contains a clock doubler 1082 to double the video clock rate of the video clock signal that it receives. The doubled video clock rate is fed into video parallel to serial converter 1082 through buffer 1083 and is sent to serial to parallel converter 980 through buffer 1084. Additionally, reset control unit 1035 in PIC 1000 receives a reset signal from the CPU CNTL & GPIO latch/driver unit 1090 and transmits the reset signal on the RESET# line to the HIC 900 whereas reset control unit 945 of HIC 900 receives the reset signal and forwards it to its CPU CNTL & GPIO latch/driver unit 990 because, in the above embodiment, the reset signal RESET# is unidirectionally sent from the PIC 1000 to the HIC 900.

Like HIC 900, PIC 1000 handles the PCI bus control signals and control bits from the XPBus representing PCI control signals in the following ways:

1. PIC 1000 buffers clocked control signals from the secondary PCI bus, encodes them and sends the encoded control bits to the XPBus;

2. PIC 1000 manages the signal locally; and

3. PIC 1000 receives control bits from XPBus, translates them into PCI control signals and sends the PCI control signals to the secondary PCI bus.

PIC 1000 also supports a reference arbiter on the secondary PCI Bus to manage the PCI signals REQ# and GNT#.

FIG. 11 is a schematic diagram of lines PCK, PD0 to PD3, and PCN. These lines are unidirectional LVDS lines for transmitting clock signals and bits from the HIC to the PIC. The bits on the PD0 to PD3 and the PCN lines are sent synchronously within every clock cycle of the PCK. Another set of lines, namely PCKR, PDR0 to PDR3, and PCNR, are used to transmit clock signals and bits from the PIC to HIC. The lines used for transmitting information from the PIC to the HIC have the same structure as those shown in FIG. 11, except that they transmit data in a direction opposite to that in which the lines shown in FIG. 11 transmit data. In other words they transmit information from the PIC to the HIC. The bits on the PDR0 to PDR3 and the PCNR lines are sent synchronously within every clock cycle of the PCKR. Some of the examples of control information that may be sent in the reverse direction, i.e., on PCNR line, include a request to switch data bus direction because of a pending operation (such as read data available), a control signal change in the target requiring communication in the reverse direction, target busy, and transmission error detected.

The XPBus which includes lines PCK, PD0 to PD3, PCN, PCKR, PDR0 to PDR3, and PCNR, has two sets of unidirectional lines transmitting clock signals and bits in opposite directions. The first set of unidirectional lines includes PCK, PD0 to PD3, and PCN. The second set of unidirectional lines includes PCKR, PDR0 to PDR3, and PCNR. Each of these unidirectional set of lines is a point-to-point bus with a fixed transmitter and receiver, or in other words a fixed master and slave bus. For the first set of unidirectional lines, the HIC is a fixed transmitter/master whereas the PIC is a fixed receiver/slave. For the second set of unidirectional lines, the PIC is a fixed transmitter/master whereas the HIC is a fixed receiver/slave. The LVDS lines of XPBus, a cable friendly and remote system I/O bus, transmit fixed length data packets within a clock cycle.

The XPBus lines, PD0 to PD3, PCN, PDR0 to PDR3 and PCNR, and the video data and clock lines, VPD and VPCK, are not limited to being LVDS lines, as they may be other forms of bit based lines. For example, in another embodiment, the XPBus lines may be IEEE 1394 lines.

It is to be noted that although each of the lines PCK, PD0 to PD3, PCN, PCKR, PDR0 to PDR3, PCNR, VPCK, and VPD is referred to as a line, in the singular rather than plural, each such line may contain more than one physical line. For example, in the embodiment shown in FIG. 11, each of lines PCK, PD0 to PD3 and PCN includes two physical lines between each driver and its corresponding receiver. The term line, when not directly preceded by the terms physical or conductive, is herein used interchangeably with a signal or bit channel of one or more physical lines for transmitting a signal. In the case of non-differential signal lines, generally one physical line is used to transmit one signal. However, in the case of differential signal lines, a pair of physical lines is used to transmit one signal. For example, a pair of physical lines together transmit a signal in a bit line or bit channel in an LVDS or IEEE 1394 interface.

A bit based line (i.e., a bit line) is a line for transmitting serial bits. Bit based lines typically transmit bit packets and use a serial data packet protocol. Examples of bit lines include an LVDS line, an IEEE 1394 line, and a Universal Serial Bus (USB) line.

In another embodiment, such as that shown in FIG. 15, the connectors on the HIC and PIC do not directly engage with one another. In the embodiment shown in FIG. 15, an extension cord 1580 having cable 1583 and connectors 1581 and 1582 disposed at the ends of cable 1583, is used to couple the connectors 1505 and 1555 on the HIC 1500 and PIC 1550, respectively. FIG. 16 is a diagram of an attached computer module 1600 with a “plug & display” port and direct power connection.

The interfaces of the present invention comprising an HIC, a PIC and the link between the HIC and PIC, either with or without an extension cord such as extension cord 1580 in FIG. 15, may be used to interface an ACM and a peripheral console. Moreover, the embodiment of the interface of the present invention having an extension cord, such as that disclosed in FIG. 15, may be used to interface two computer systems. Therefore, the interface of the present invention has broader application than that of interfacing an ACM and a peripheral console.

In one embodiment, the connectors may be limited to pins for transmitting PCI related signals. In such an embodiment, the cable would consist of conductive lines on the XPBus. In another embodiment, however, the connectors may include pins for transmitting video and/or power related signals in addition to the PCI related signals, in which case, the cable would have conductive lines for the video bus and/or power bus.

The above embodiments are described generally in terms of hardware and software. It will be recognized, however, that the functionality of the hardware can be further combined or even separated. The functionality of the software can also be further combined or even separated. Hardware can be replaced, at times, with software. Software can be replaced, at times, with hardware. Accordingly, the present embodiments should not be construed as limiting the scope of the claims here. One of ordinary skill in the art would recognize other variations, modifications, and alternatives.

While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.

Claims

1. A computer module, said module comprising:

an enclosure, said enclosure comprising a first connector configured to couple to a second connector through a cable, said second connector being insertable into a console;

a central processing unit in said enclosure, said central processing unit comprising a microprocessor based integrated circuit chip and an interface controller integrated in said chip, said interface controller being configured to transmit and receive serial bits of peripheral component Interconnect (“PCI”) bus transaction, said serial bits of PCI bus transaction comprising PCI address and data bits;

a low voltage differential signal (“LVDS”) channel in said enclosure, said LVDS channel comprising a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction, said LVDS channel directly extending from said interface controller to convey said serial bits of PCI bus transaction;

a hard disk drive in said enclosure, said hard disk drive being coupled to said central processing unit; and

a programmable memory device in said enclosure, said programmable memory device being configurable to store a password for preventing a possibility of unauthorized use of said hard disk drive.

2. The computer module of claim 1 further comprising a host interface controller for providing a status of a locking device in said enclosure.

3. The computer module of claim 1 further comprising a mechanical locking device that is coupled to said programmable memory device.

4. The computer module of claim 1 further comprising a host interface controller coupled to a mechanical locking device, said host interface controller being coupled to said programmable memory device.

5. The computer module of claim 1 wherein said programmable memory device comprises a flash memory device.

6. The computer module of claim 1 wherein said programmable memory device comprises a flash memory device having at least 8 Mbits of cells and greater.

7. The computer module of claim 1 further comprising a security program in a main memory.

8. The computer module of claim 7 wherein said security program comprises a code for storing a password on said programmable memory device.

9. The computer module of claim 8 wherein said security program comprises a code for checking a time from said real-time clock circuit.

10. The computer module of claim 1 further comprising a host interface controller coupled to a solenoid that drives a mechanical lock in a first position to a second position.

11. The computer module of claim 10 wherein said solenoid also drives said mechanical lock from said second position to said first position.

12. The computer module of claim 1 further comprising a real-time clock circuit coupled to said central processing unit.

13. The computer module of claim 12 further comprising a battery coupled to a host interface controller that includes said real-time clock.

14. A method for operating a computer system, said method comprising:

inserting an attached computer module (“ACM”) into a bay of a console of a modular computer system, said ACM comprising

a low voltage differential signal (“LVDS”) channel comprising at least two unidirectional serial bit channels to convey data in opposite directions; and

a microprocessor unit coupled to a mass memory storage device, said microprocessor unit comprising an interface controller coupled to said LVDS channel to communicate peripheral component Interconnect (“PCI”) bus transaction in serial form over said LVDS channel;

applying power to said computer system and said ACM to execute a security program, said security program being stored in said mass memory storage device; and

prompting for a user password from a user on a display.

15. The method of claim 14 wherein said ACM comprises an enclosure that houses said microprocessor unit and said mass memory storage device.

16. The method of claim 14 further comprising providing a user password to said security program.

17. The method of claim 14 further comprising wherein said mass memory storage device comprises a flash memory device for storing a desired password for said ACM.

18. The method of claim 17 wherein said flash memory device maintains said desired password when power is removed from said ACM.

19. The method of claim 18 wherein said flash memory device is coupled to a host interface controller that is coupled to said microprocessor based unit.

20. The method of claim 14 wherein said mass memory storage device comprises a code directed to comparing said user password with a desired password.

21. The method of claim 14 further comprising identifying a permanent password or user code on said attached computer module.

22. The method of claim 21 wherein said permanent password or user code is stored in said microprocessor unit.

23. The method of claim 21 wherein said permanent password or user code is stored in a flash memory device coupled to said microprocessor unit.

24. The computer module of claim 1 wherein said central processing unit comprises a graphics controller integrated in said chip.

25. The computer module of claim 24 wherein said console comprises a display, and said graphics controller is configured to couple to said display upon insertion of said second connector into said console.

26. The computer module of claim 1 wherein said interface controller is configured to output encoded address and data bits of PCI bus transaction in serial form that are conveyed over said LVDS channel.

27. The computer module of claim 1 wherein said LVDS channel corresponds to a first LVDS channel, said console comprises a second LVDS channel, and said first LVDS channel is configured to couple to said second LVDS channel upon insertion of said second connector into said console.

28. The method of claim 14 wherein said interface controller is configured to output an encoded serial bit stream of PCI address and data information, said LVDS channel directly extends from said interface controller, and further comprising conveying said encoded serial bit stream over said LVDS channel.

29. The method of claim 14 wherein said microprocessor unit comprises a graphics controller integrated with said microprocessor unit in a single chip, and further comprising coupling said graphics controller to said display upon insertion of said ACM.

30. A computer module, said module comprising:

an enclosure, said enclosure comprising a first connector configured to couple to a second connector through a cable, said second connector being insertable into a console, said console comprising a universal serial bus;

a central processing unit in said enclosure, said central processing unit comprising a microprocessor based integrated circuit chip and an interface controller integrated in said chip;

a low voltage differential signal (“LVDS”) channel directly extending from said interface controller, said LVDS channel comprising two sets of unidirectional serial bit channels to convey data in opposite directions;

a hard disk drive in said enclosure, said hard disk drive being coupled to said central processing unit; and

a programmable memory device in said enclosure, said programmable memory device being configurable to store a password for preventing a possibility of unauthorized use of said hard disk drive.

31. The computer module of claim 30 wherein said interface controller is configured to output an encoded serial bit stream that is conveyed over said LVDS channel.

32. The computer module of claim 31 wherein said encoded serial bit stream is conveyed over said LVDS channel as 10-bit packets.

33. The computer module of claim 31 wherein said encoded serial bit stream comprises encoded address and data bits of peripheral component Interconnect (“PCI”) bus transaction.

34. The computer module of claim 31 wherein said encoded serial bit stream comprises information of universal serial bus protocol.

35. The computer module of claim 34 wherein said LVDS channel is configured to couple to said universal serial bus upon insertion of said second connector into said console.

36. The computer module of claim 31 further comprising a main memory in said enclosure, said main memory being directly coupled to said central processing unit.

37. A computer module, said module comprising:

an enclosure, said enclosure comprising a first connector configured to couple to a second connector through a cable, said second connector being insertable into a console, said console comprising a mass storage device and a first channel comprising two low voltage differential signal (“LVDS”), unidirectional serial bit channels to convey data in opposite directions;

a central processing unit in said enclosure, said central processing unit comprising a microprocessor based integrated circuit chip and an interface controller integrated in said chip, said interface controller being configured to communicate address and data of peripheral component Interconnect (“PCI”) bus transaction in serial form;

a second channel directly coupled to said interface controller, said second channel comprising two LVDS, unidirectional, multiple serial bit channels to convey data in opposite directions;

a hard disk drive in said enclosure, said hard disk drive being coupled to said central processing unit; and

a programmable memory device in said enclosure, said programmable memory device being configurable to store a password for preventing a possibility of unauthorized use of said hard disk drive.

38. The computer module of claim 37 wherein, upon insertion of said second connector into said console, said first channel is configured to couple to said second channel to communicate said address and data of PCI bus transaction.

39. The computer module of claim 37 wherein, upon insertion of said second connector into said console, said central processing unit is configured to couple to said mass storage device through said first channel and said second channel.

40. The computer module of claim 37 wherein said interface controller is configured to output said address and data of PCI bus transaction as 10-bit packets that are conveyed over said second channel.

41. The computer module of claim 37 further comprising a main memory in said enclosure, said main memory being directly coupled to said central processing unit.

42. A computer module, said module comprising:

an enclosure, said enclosure comprising a first connector configured to couple to a second connector through a cable, said second connector being insertable into a console, said console comprising a mass storage device and a first channel comprising two low voltage differential signal (“LVDS”), unidirectional serial bit channels to convey data in opposite directions;

a central processing unit in said enclosure, said central processing unit comprising a microprocessor based integrated circuit chip;

a second channel in said enclosure, said second channel comprising two LVDS, unidirectional, multiple serial bit channels to convey data in opposite directions;

a peripheral bridge to communicate address and data of peripheral component Interconnect (“PCI”) bus transaction in serial form over said second channel, said peripheral bridge coupled to said central processing unit without any intervening PCI bus;

a hard disk drive in said enclosure, said hard disk drive being coupled to said central processing unit; and

a programmable memory device in said enclosure, said programmable memory device being configurable to store a password for preventing a possibility of unauthorized use of said hard disk drive.

43. The computer module of claim 42 wherein, upon insertion of said second connector into said console, said first channel is configured to couple to said second channel to communicate said address and data of PCI bus transaction.

44. The computer module of claim 42 wherein, upon insertion of said second connector into said console, said central processing unit is configured to couple to said mass storage device through said second channel.

45. The computer module of claim 42 wherein said second channel directly extends from said peripheral bridge.

46. The computer module of claim 45 wherein said peripheral bridge is configured to output said address and data of PCI bus transaction as 10-bit packets that are conveyed over said second channel.

47. A computer module, said module comprising:

an enclosure, said enclosure comprising a first connector configured to couple to a second connector through a cable, said second connector being insertable into a console;

a central processing unit in said enclosure, said central processing unit comprising a microprocessor based integrated circuit chip and an interface controller integrated in said chip, said interface controller being configured to transmit and receive serial bits of peripheral component Interconnect (“PCI”) bus transaction as 10-bit packets, said serial bits of PCI bus transaction comprising encoded PCI address and data bits;

a low voltage differential signal (“LVDS”) channel in said enclosure, said LVDS channel comprising a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction, said LVDS channel directly extending from said interface controller to convey said serial bits of PCI bus transaction;

a hard disk drive in said enclosure, said hard disk drive being coupled to said central processing unit; and

a programmable memory device in said enclosure, said programmable memory device being configurable to store a password for preventing a possibility of unauthorized use of said hard disk drive.

48. The computer module of claim 47 wherein said console comprises a mass storage device, and, upon insertion of said second connector into said console, said central processing unit is configured to communicate with said mass storage device through said LVDS channel.

49. The computer module of claim 47 wherein said LVDS channel extends through said first connector to convey said serial bits of PCI bus transaction between said computer module and said console.

50. The computer module of claim 47 wherein said console comprises a display, and said first connector is configured to convey video signals between said computer module and said console.

51. The computer module of claim 50 wherein said central processing unit comprises a graphics controller integrated in said chip.

52. The computer module of claim 51 wherein said graphics controller is configured to communicate with said display through said first connector.

53. A method for operating a computer system, said method comprising:

inserting an attached computer module (“ACM”) into a bay of a console of a modular computer system, said console comprising an input device, said ACM comprising

a microprocessor unit coupled to a mass memory storage device, said microprocessor unit comprising an interface controller to communicate peripheral component Interconnect (“PCI”) bus transaction in serial form; and

a low voltage differential signal (“LVDS”) channel comprising at least two unidirectional serial bit channels to convey data in opposite directions, said LVDS channel directly extending from said interface controller to convey said PCI bus transaction in serial form;

conveying data packets of universal serial bus protocol between said ACM and said console;

applying power to said computer system and said ACM to execute a security program, said security program being stored in said mass memory storage device; and

prompting for a user password from a user on a display.

54. The method of claim 53 wherein said interface controller is configured to output a serial bit stream of PCI address and data information, and further comprising conveying said serial bit stream over said LVDS channel.

55. The method of claim 53 wherein said mass memory storage device comprises a flash memory device.

56. The method of claim 53 wherein conveying said data packets of universal serial bus protocol comprises conveying said data packets over serial bit lines.

57. The method of claim 53 wherein conveying said data packets of universal serial bus protocol comprises conveying said data packets between said ACM and said input device.

58. The method of claim 53 wherein said microprocessor unit comprises a graphics controller integrated with said microprocessor unit in a single chip, and further comprising coupling said graphics controller to said display upon insertion of said ACM.

59. The computer module of claim l wherein said LVDS channel extends through said first connector to convey said serial bits of PCI bus transaction between said computer module and said console.