Data security method and device for computer modules

Abstract

A security method for an attached computer module in a computer system. The security method reads a security identification number in an attached computer module and compares it to a security identification number in a console, which houses the attached computer module. Based upon a relationship between these numbers, a security status is selected. The security status determines the security level of operating the computer system.

Description

FIG. 9 depicts a peripheral console configuration.

temper

The reserved data packet types can be used to support non-PCI bus transactions, e.g., USB transactions. The bits sent in the first nibble of each data packet indicate the type of the data packet. FIG. 24 is a table showing different types of first nibbles and their corresponding data packet types.

Although the functionality above has been generally described in terms of a specific sequence of steps, other steps can also be used. Here, the steps can be implemented in a combination of hardware, firmware, and software. Either of these can be further combined or even separated. Depending upon the embodiment, the functionality can be implemented in a number of different ways without departing from the spirit and scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives.

FIG. 25 is a table showing the information transmitted on the XPBus during two clock cycles of the XPBus in one embodiment of the present invention where 10 data bits are transmitted in each clock cycle of the XPBus. In FIG. 25, A00 to A31 represent 32 bits of PCI address A[31::0], D00 to D31 represent 32 bits of PCI data D[31::0], BS0 to BS3 represent 4 bits of bus status data indicating the status of the XPBus, CM0# to CM3# represent 4 bits of PCI command information, BE0# to BE3# represent 4 bits of PCI byte enable information, and CN0 to CN9 represent 10 bits of control information sent in each clock cycle. As shown in FIG. 25, for each of lines PD0 to PD3, the 10 bit data packets contain one BS bit, one CM/BE bit, and eight A/D bits. For the PCN line, the 10 bit data packet contains 10 CN bits. The first clock cycle shown in FIG. 25 comprises an address cycle in which 4 BS bits, 4 CM bits, 32 A bits and 10 CN bits are sent. The second clock cycle comprises a data cycle in which 4 BS bits, 4 BE bits, 32 D bits and 10 CN bits are sent. The bits transmitted on lines PD0 to PD3 represent 32 PCI AD[31::0] signals, 4 PCI C/BE# [3::0] signals, and part of the function of PCI control signals, such as FRAME#, IRDY#, and TRDY#.

In the embodiment shown in FIG. 25, BS0 to BS3 are sent at the beginning of each clock cycle. The bus status bits indicate the following bus cycle transactions: idle, address transfer, write data transfer, read data transfer, switch XPBus direction, last data transfer, wait, and other cycles.

FIG. 26 is a more detailed block diagram of one embodiment of an HIC 26505 and PIC 26555 of the present invention. HIC 26505 includes a peripheral component interconnect (PCI) bus controller 510, an XPBus controller 26515. a phase lock loop (PLL) clock 520 and an input/output (IO) control 525. Similarly, PIC 26555 includes a PCI bus controller 560, an XPBus controller 26565, a PLL clock 570 and an IO control 575. PCI bus controllers 510 and 560 are coupled to the primary and secondary PCI buses 530 and 580, respectively, and manage PCI transactions on the primary and secondary PCI buses 530 and 580, respectively. Similarly, XPBus Controllers 26515 and 26565 are coupled to XPBus 590. XPBus controller 26515 drives the PCK line 591 and PD[0::3] and PCN lines 592 while XPBus controller 26565 drives the PCKR lines 593, the PDR[0::3] and PCNR lines 594 and the RESET# line 595.

PCI bus controller 510 receives PCI clock signals from the primary PCI bus 530 and is synchronized to the PCI clock. However, as indicated in FIG. 26, the XPBus controller 26515 is asynchronous with the PCI bus controller 510. Instead, the XPBus controller receives a clock signal from the PLL clock 520 and is synchronized therewith. PLL clock 520 generates a clock signal independent of the PCI clock. The asynchronous operation of the PCI bus and the XPBus allows the PCI Bus to change in frequency, for example as in a power down situation, without directly affecting the XPBus clocking. In the embodiment shown in FIG. 26, the PLL clock 520 generates a clock signal having a frequency of 66 MHz, which is twice as large as the 33 MHz frequency of the PCI clock. (The clock signal generated by the PLL clock may have a clock speed different from, including lower than, 66 MHz. For example, in another embodiment, which is discussed in greater detail below, the PLL clock 520 generates a clock signal having a frequency of 132 MHz.)

While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.

Claims

1. A security protection method for a computer module, said method comprising:

inserting the computer module into a console;

initiating a security program in said module to read a security identification of said console and to read a security identification of said computer module;

determining of a predetermined security status based upon a relationship of said console identification and said computer module identification;

selecting said predetermined security status; and

operating said computer module based upon said security status.

2. The method of claim 1 wherein said predetermined security status disables a network access to the computer module.

3. The method of claim 1 wherein said predetermined security status disables a secondary storage of information from said computer module to substantially prevent information to be transferred from a memory of the computer module to said secondary storage.

4. The method of claim 1 wherein said security program is provided in a system BIOS.

5. The method of claim 1 wherein said step of initiating reads said security identification of said computer module from a flash memory device.

6. The method of claim 1 wherein said step of initiating reads said security identification of said console from a flash memory device.

7. The method of claim 1 wherein said console is selected from a desktop home computing device, an office desktop computing device, a mobile computing device, a television sot-top computing device, and a co-worker's computing device.

8. A system for secured information transactions, the system comprising:

a console comprising a peripheral controller housed in the console;

a user identification input device coupled to the peripheral controller, the user identification input device being provided for user identification data; and

an attached computer module coupled to the console, the attached computer module comprising a security memory device stored with the user identification data.

9. The system of claim 8 wherein the user identification input device is a finger print reader.

10. The system of claim 8 wherein the user identification input device is a voice processing device.

11. A method for operating a module computer into one of a plurality of network systems, the method comprising:

providing a computer module, the module comprising a connection program;

inserting the computer module into a computer console, the computer console having access to a network;

receiving connection information from the computer console;

configuring the connection program to adapt to the connection information; and

establish a connection between the computer module and a server coupled to the network.

12. The method of claim 11 wherein the connection information comprises a connection protocol for providing the connection.

13. The method of claim 12 wherein the connection protocol is selected from TCP/IP, or mobile IP.

14. A computer system, comprising:

a central processing unit (CPU);

a low voltage differential signal (lvds) channel directly extending from the CPU, the lvds channel comprising two unidirectional, serial bit channels to convey data in opposite directions; and

a mass storage device directly coupled to the CPU;

wherein the CPU is configured to output a serial bit stream of Universal Serial bus (USB) protocol information that is conveyed over the lvds channel.

15. The computer system of claim 14 wherein the mass storage device comprises flash memory.

16. The computer system of claim 14 further comprising a second lvds channel extending directly from the CPU, comprising two unidirectional, serial bit channels to convey data in opposite directions.

17. The computer system of claim 16 wherein the serial bit channels conveys address and data bits of a peripheral component interface (PCI) bus transaction.

18. The computer system of claim 17 wherein the second lvds channel couples to the mass storage device.

19. A computer system, comprising:

a central processing unit (CPU);

a mass storage device directly coupled to the CPU; and

a low voltage differential signal (lvds) channel directly extending from the CPU, the lvds channel comprising two unidirectional, serial bit channels to convey data in opposite directions;

wherein the lvds channel is configured to output a serial bit stream of address bits, data bits, and byte enable information bits of a peripheral component interface (PCI) bus transaction.

20. The computer system of claim 19, wherein the mass storage device comprises flash memory.

21. The computer system of claim 19, wherein the lvds channel couples to the mass storage device.

22. The computer system of claim 19 wherein the CPU comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the lvds channel to convey the serial bit stream of address and data bits of the PCI bus transaction.

23. The computer system of claim 22 wherein the interface controller generates different data transfer rates to convey serial bit streams of address and data bits of PCI bus transactions through the lvds channel based on different clock frequencies generated by the PLL clock circuitry.

24. The computer system of claim 19 wherein the central processing unit (CPU) comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the lvds channel to convey said PCI bus transaction.

25. The computer system of claim 24 wherein the interface controller generates different data transfer rates to convey the PCI bus transaction through the lvds channel based on different clock frequencies generated by the PLL clock circuitry.

26. A computer system, comprising:

an integrated central processing unit and graphics subsystem in a single chip directly connected to a low voltage differential signal (lvds) channel to convey encoded address and data bits of a peripheral component Interconnect (PCI) bus transaction in serial form, wherein the lvds channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; and

a mass storage device directly coupled to the integrated central processing unit and graphics subsystem, comprising flash memory;

wherein the integrated central processing unit and graphics subsystem directly outputs a differential signal channel to convey digital video display signals.

27. The computer system of claim 26 wherein the differential signal channel conveys Transition Minimized differential Signaling (TMDS) signals.

28. The computer system of claim 26 wherein the lvds channel couples to the mass storage device.

29. A computer system, comprising:

a printed circuit board coupled to a connector;

a central processing unit (CPU);

a first low voltage differential signal (lvds) channel directly extending from the CPU, the lvds channel comprising two sets of unidirectional, serial bit channels to convey an encoded serial bit stream of address bits, data bits, and byte enable information bits of a peripheral component Interconnect (PCI) bus transaction in opposite directions;

a mass storage device coupled to the CPU; and

a second lvds channel coupled to the connector, comprising two sets of unidirectional, serial bit channels to convey serial bit data in opposite directions.

30. The computer system of claim 29 wherein the second lvds channel communicates Ethernet protocol signals.

31. The computer system of claim 29 further comprising a graphics subsystem integrated with the CPU as a single chip, and wherein the integrated central processing unit and graphics subsystem directly outputs a differential signal channel to convey digital video display signals.

32. A computer system, comprising:

an integrated central processing unit and graphics subsystem in a single chip directly outputting digital video display signals to a differential signal channel; and

a low voltage differential signal (lvds) channel to convey Universal Serial bus (USB) protocol signals, wherein the lvds channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction;

wherein the differential signal channel conveys Transition Minimized differential Signaling (TMDS) signals.

33. The computer system of claim 32 further comprising a mass storage device directly coupled to the integrated central processing unit and graphics subsystem.

34. The computer system of claim 33, wherein the mass storage device comprises flash memory.

35. A computer system, comprising:

a printed circuit board coupled to a connector;

a central processing unit;

a mass storage unit coupled to the central processing unit;

a first low voltage differential signal (lvds) channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions; and

a peripheral bridge directly coupled to the central processing unit without any intervening peripheral component Interconnect (PCI) bus, wherein the peripheral bridge directly conveys an encoded serial bit stream of address bits, data bits, and byte enable information bits of a PCI bus transaction over the first lvds channel; and

a second lvds channel coupled to the connector, comprising two sets of unidirectional, serial bit channels to convey serial bit data in opposite directions.

36. The computer system of claim 35 wherein the second lvds channel communicates Ethernet protocol signals.

37. The computer system of claim 35 wherein the mass storage device comprises flash memory, directly coupled to the central processing unit through a third lvds channel comprising two sets of unidirectional, serial bit channels to convey data in opposite directions.

38. The computer system of claim 35 wherein the peripheral bridge comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the first lvds channel to convey encoded serial bit streams of address and data bits of PCI bus transactions.

39. The computer system of claim 38 wherein the interface controller generates different data transfer rates to convey the encoded serial bit streams of address and data bits of the PCI bus transactions through the first lvds channel based on different clock frequencies generated by the PLL clock circuitry.

40. The computer system of claim 35 wherein the peripheral bridge comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the first lvds channel to convey said PCI bus transaction.

41. The computer system of claim 40 wherein the interface controller generates different data transfer rates to convey the PCI bus transaction through the lvds channel based on different clock frequencies generated by the PLL clock circuitry.

42. A computer, comprising:

a central processing unit directly coupled to a first low voltage differential signal (lvds) channel comprising at least two sets of unidirectional, serial bit channels to convey encoded address and data bits of a peripheral component Interconnect (PCI) bus transaction in serial bit streams in opposite directions;

a graphics subsystem directly coupled to a differential signal channel to convey digital video display signals;

a connector coupled to the central processing unit through a second low voltage differential signal (lvds) channel comprising two unidirectional, differential signal pairs to convey serial bit data in opposite directions.

43. The computer of claim 42 wherein the CPU and graphics subsystem are integrated on a single chip.

44. The computer of claim 43 wherein the second lvds channel conveys an encoded serial bit stream of address and data bits of a PCI bus transaction.

45. The computer of claim 42 wherein the second lvds channel conveys an encoded serial bit stream of address and data bits of a PCI bus transaction.

46. The computer of claim 45 wherein the connector further conveys digital video display signals through a differential signal channel, and the connector is configured for coupling to a console through a cable.

47. The computer of claim 42 further comprising a mass storage device directly coupled to the central processing unit, wherein the mass storage device comprises flash memory.

48. A computer system comprising:

a central processing unit (CPU) comprising an interface controller;

a first low voltage differential signal (lvds) channel directly extending from the interface controller, the first lvds channel comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channel comprises four or more differential signal pairs; and

a second lvds channel coupled to a connector, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions;

wherein the first lvds channel conveys encoded serial bit streams of address bits, data bits, and byte enable information bits of peripheral component Interconnect (“PCI”) bus transactions.

49. The computer system of claim 48 wherein the interface controller is coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller generates different data transfer rates to convey PCI bus transactions through the first lvds channel based on different clock frequencies generated by the PLL clock circuitry.

50. The computer system of claim 49 wherein the second lvds channel communicates Ethernet protocol traffic.

51. A computer system comprising:

a central processing unit (CPU);

a peripheral bridge directly coupled to the CPU without any intervening peripheral component Interconnect (PCI) bus;

a first low voltage differential signal (lvds) channel directly coupled to the peripheral bridge, comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channels comprises four or more differential signal pairs; and

a second lvds channel extending directly from the CPU, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions;

wherein the first lvds channel conveys encoded serial bit streams of address bits, data bits, and byte enable information bits of PCI bus transactions.

52. The computer system of claim 51 wherein the peripheral bridge comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller directly couples to the first lvds channel to convey said PCI bus transactions.

53. The computer system of claim 52 wherein the interface controller generates different data transfer rates to convey said PCI bus transactions through the first lvds channel based on different clock frequencies generated by the PLL clock circuitry.

54. A computer system comprising:

a central processing unit (CPU) comprising an interface controller;

a first low voltage differential signal (lvds) channel directly extending from the interface controller, the first lvds channel comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channel comprises four or more differential signal pairs; and

a second lvds channel coupled to a connector, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions; and

wherein the first lvds channel conveys an encoded serial bit stream of address and data bits of a peripheral component Interconnect (“PCI”) bus transaction.

55. The computer system of claim 54 wherein the interface controller is coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller generates different data transfer rates to convey the PCI bus transaction through the first lvds channel based on different clock frequencies generated by the PLL clock circuitry.

56. The computer system of claim 55 wherein the second lvds channel communicates Ethernet protocol.

57. A computer system comprising:

a central processing unit (CPU);

a peripheral bridge directly coupled to the CPU without any intervening peripheral component Interconnect (PCI) bus;

a first low voltage differential signal (lvds) channel directly coupled to the peripheral bridge, comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channel comprises four or more differential signal pairs; and

a second lvds channel extending directly from the CPU, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions;

wherein the first lvds channel conveys an encoded serial bit stream of address and data bits of a PCI bus transaction.

58. The computer system of claim 57 wherein the peripheral bridge comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the first lvds channel to convey said PCI bus transaction.

59. The computer system of claim 58 wherein the interface controller generates different data transfer rates to convey the PCI bus transaction through the lvds channel based on different clock frequencies generated by the PLL clock circuitry.

60. A computer comprising:

a connector for external peripheral data communication;

a central processing unit (CPU);

a first low voltage differential signal (lvds) channel directly connected to the CPU comprising two unidirectional, serial bit channels that transmit data in opposite directions; and

a second lvds channel to convey Universal Serial bus (USB) protocol traffic through the connector, the second lvds channel including two unidirectional, serial bit channels that transmit data in opposite direction; and

wherein the connector further conveys digital video data through a third differential signal channel.

61. The computer of claim 60 wherein the first lvds channel conveys address and data bits, and byte enable information bits of a peripheral component Interconnect (PCI) bus transaction in serial form.

62. A computer comprising:

a connector for external peripheral data communication;

an integrated central processing unit and graphics subsystem in a single chip; and

a first low voltage differential signal (lvds) channel comprising two unidirectional, serial bit channels that transmit data in opposite directions;

wherein the integrated graphics subsystem directly outputs digital video display data to a unidirectional differential signal channel;

wherein the first lvds channel conveys Universal Serial bus (USB) protocol traffic through the connector and wherein the digital video display data couples to the connector.

63. The computer of claim 62 wherein the digital video display data is transmitted through Transition Minimized differential Signaling (TMDS).