Data security method and device for computer modules

Abstract

A security method for an attached computer module in a computer system. The security method reads a security identification number in an attached computer module and compares it to a security identification number in a console, which houses the attached computer module. Based upon a relationship between these numbers, a security status is selected. The security status determines the security level of operating the computer system.

Description

FIG. 9 depicts a peripheral console configuration.temper

FIG. 16 is a schematic diagram of lines PCK, PD0 to PD3, and PCN. These lines are unidirectional LVDS lines for transmitting clock signals and bits from the HIC to the PIC. The bits on the PD0 to PD3 and the PCN lines are sent synchronously within every clock cycle of the PCK. Another set of lines, namely PCKR, PDR0 to PDR3, and PCNR, are used to transmit clock signals and bits from the PIC to HIC. The lines used for transmitting information from the PIC to the HIC have the same structure as those shown in FIG. 16, except that they transmit data in a direction opposite to that in which the lines shown in FIG. 16 transmit data. In other words they transmit information from the PIC to the HIC. The bits on the PDR0 to PDR3 and the PCNR lines are sent synchronously within every clock cycle of the PCKR. Some of the examples of control information that may be sent in the reverse direction, i.e., on PCNR line, include a request to switch data bus direction because of a pending operation (such as read data available), a control signal change in the target requiring communication in the reverse direction, target busy, and transmission error detected.

The XPBus which includes lines PCK, PD0 to PD3, PCN, PCKR, PDR0 to PDR3, and PCNR, has two sets of unidirectional lines transmitting clock signals and bits in opposite directions. The first set of unidirectional lines includes PCK, PD0 to PD3, and PCN. The second set of unidirectional lines includes PCKR, PDR0 to PDR3, and PCNR. Each of these unidirectional set of lines is a point-to-point bus with a fixed transmitter and receiver, or in other words a fixed master and slave bus. For the first set of unidirectional lines, the HIC is a fixed transmitter/master whereas the PIC is a fixed receiver/slave. For the second set of unidirectional lines, the PIC is a fixed transmitter/master whereas the HIC is a fixed receiver/slave. The LVDS lines of XPBus, a cable friendly and remote system I/O bus, transmit fixed length data packets within a clock cycle.

The XPBus lines, PD0 to PD3, PCN, PDR0 to PDR3 and PCNR, and the video data and clock lines, VPD and VPCK, are not limited to being LVDS lines, as they may be other forms of bit based lines. For example, in another embodiment, the XPBus lines may be IEEE 1394 lines.

It is to be noted that although each of the lines PCK, PD0 to PD3, PCN, PCKR, PDR0 to PDR3, PCNR, VPCK, and VPD is referred to as a line, in the singular rather than plural, each such line may contain more than one physical line. For example, in the embodiment shown in FIG. 16, each of lines PCK, PD0 to PD3 and PCN includes two physical lines between each driver and its corresponding receiver. The term line, when not directly preceded by the terms physical or conductive, is herein used interchangeably with a signal or bit channel of one or more physical lines for transmitting a signal. In the case of non-differential signal lines, generally only one physical line is used to transmit one signal. However, in the case of differential signal lines, a pair of physical lines is used to transmit one signal. For example, a pair of physical lines together transmit a signal in a bit line or bit channel in an LVDS or IEEE 1394 interface.

A bit based line (i.e., a bit line) is a line for transmitting serial bits. Bit based lines typically transmit bit packets and use a serial data packet protocol. Examples of bit lines include an LVDS line, an IEEE 1394 line, and a Universal Serial Bus (USB) line.

Although the functionality above has been generally described in terms of a specific sequence of steps, other steps can also be used. Here, the steps can be implemented in a combination of hardware, firmware, and software. Either of these can be further combined or even separated. Depending upon the embodiment, the functionality can be implemented in a number of different ways without departing from the spirit and scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives.

While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.

Claims

1. A security protection method for a computer module, said method comprising:

inserting the computer module into a console;

initiating a security program in said module to read a security identification of said console and to read a security identification of said computer module;

determining of a predetermined security status based upon a relationship of said console identification and said computer module identification;

selecting said predetermined security status; and

operating said computer module based upon said security status.

2. The method of claim 1 wherein said predetermined security status disables a network access to the computer module.

3. The method of claim 1 wherein said predetermined security status disables a secondary storage of information from said computer module to substantially prevent information to be transferred from a memory of the computer module to said secondary storage.

4. The method of claim 1 wherein said security program is provided in a system BIOS.

5. The method of claim 1 wherein said step of initiating reads said security identification of said computer module from a flash memory device.

6. The method of claim 1 wherein said step of initiating reads said security identification of said console from a flash memory device.

7. The method of claim 1 wherein said console is selected from a desktop home computing device, an office desktop computing device, a mobile computing device, a television sot-top computing device, and a co-worker's computing device.

8. A system for secured information transactions, the system comprising:

a console comprising a peripheral controller housed in the console;

a user identification input device coupled to the peripheral controller, the user identification input device being provided for user identification data; and

an attached computer module coupled to the console, the attached computer module comprising a security memory device stored with the user identification data.

9. The system of claim 8 wherein the user identification input device is a finger print reader.

10. The system of claim 8 wherein the user identification input device is a voice processing device.

11. A method for operating a module computer into one of a plurality of network systems, the method comprising:

providing a computer module, the module comprising a connection program;

inserting the computer module into a computer console, the computer console having access to a network;

receiving connection information from the computer console;

configuring the connection program to adapt to the connection information; and

establish a connection between the computer module and a server coupled to the network.

12. The method of claim 11 wherein the connection information comprises a connection protocol for providing the connection.

13. The method of claim 12 wherein the connection protocol is selected from TCP/IP, or mobile IP.

14. A system for information transactions, the system comprising:

a console comprising

a power supply connection, and

a first low voltage differential signal (lvds) channel comprising two sets of unidirectional, serial bit channels to convey address and data bits of peripheral component interface (PCI) bus transaction in opposite directions; and

a computer module configured to couple to the console, the computer module comprising

a central processing unit (CPU) comprising an interface controller integrated with the CPU as a single chip,

a main memory directly coupled to the CPU,

a mass storage device directly coupled to the CPU, and

a second lvds channel directly extending from the CPU, the second lvds channel comprising two sets of unidirectional, serial bit channels to convey data in opposite directions,

wherein the CPU is configured to couple to the console through the second lvds channel, and

wherein the computer module is configured to receive power from the power supply connection upon coupling of the computer module to the console.

15. The system of claim 14, wherein the computer module is configured to couple to the console as a “plug and play” operation.

16. The system of claim 14, wherein the interface controller is configured to output a serial bit stream that is conveyed over the second lvds channel.

17. The system of claim 16, wherein the serial bit stream comprises address and data bits of PCI bus transaction.

18. The system of claim 16, wherein the serial bit stream comprises information of Universal serial Bus protocol.

19. The system of claim 14, wherein the console further comprises an enclosure with a connector on one side, and the connector is coupled to the first lvds channel.

20. The system of claim 19, wherein the first lvds channel is configured to couple to the second lvds channel upon coupling of the computer module to the connector.

21. A system for information transactions, the system comprising:

a computer module configured to couple to a console, the computer module comprising

a central processing unit (CPU) comprising an interface controller integrated with the CPU as a single chip,

a main memory directly coupled to the CPU, and

a low voltage differential signal (lvds) channel directly extending from the interface controller, the lvds channel comprising two sets of unidirectional, serial bit channels to convey data in opposite directions,

wherein the CPU is configured to couple to the console through the lvds channel.

22. The system of claim 21, further comprising the console comprising a power supply connection, and the computer module is configured to receive power from the power supply connection upon coupling of the computer module to the console.

23. The system of claim 21, further comprising the console comprising a Liquid Crystal Display.

24. The system of claim 23, wherein the computer module further comprises a graphics controller configured to couple to the Liquid Crystal Display upon coupling of the computer module to the console.

25. The system of claim 24, wherein the graphics controller is configured to output video data that is conveyed to the Liquid Crystal Display upon coupling of the computer module to the console.

26. The system of claim 25, wherein the computer module further comprises an enclosure with a connector on one side, the connector is coupled to the lvds channel, and the CPU is configured to couple to the console through the connector.

27. The system of claim 26, wherein the connector is coupled to the graphics controller to convey the video data.

28. The system of claim 21, wherein the interface controller is configured to output address and data bits of PCI bus transaction in serial form that are conveyed over the lvds channel.

29. The system of claim 21, wherein the interface controller is configured to output data packets of Universal serial Bus protocol that are conveyed over the lvds channel.

30. A system for information transactions, the system comprising:

a computer module configured to couple to a console, the computer module comprising

a central processing unit (CPU) comprising a serial interface and a graphics controller integrated with the CPU as a single chip, the serial interface configured to transmit and receive serial bits of bus transaction,

a main memory coupled to the CPU, and

a low voltage differential signal (lvds) channel comprising at least two unidirectional, serial bit channels to convey data in opposite directions, the lvds channel directly extending from the CPU to convey the serial bits of bus transaction as data packets,

wherein the computer module is configured to couple to the console through the lvds channel.

31. The system of claim 30, further comprising the console comprising a user identification input device to provide user identification data.

32. The system of claim 31, wherein the computer module further comprises a memory device to store the user identification data.

33. The system of claim 30, wherein the computer module is configured to couple to the console as a “plug and play” operation.

34. The system of claim 30, wherein the serial bits comprise address and data bits of PCI bus transaction.

35. The system of claim 30, wherein the serial bits comprise information of Universal serial Bus protocol.

36. The system of claim 30, wherein the computer module further comprises an enclosure with a connector on one side, the connector is coupled to the lvds channel, and the computer module is configured to couple to the console through the connector.

37. The system of claim 36, wherein the connector is coupled to the graphics controller to convey video data.

38. A system for information transactions, the system comprising:

a console comprising a first interface controller; and

a computer module configured to couple to the console, the computer module comprising

a central processing unit (CPU) comprising a second interface controller integrated with the CPU as a single chip,

a main memory coupled to the CPU,

a mass storage device coupled to the CPU, the mass storage device comprising a flash memory device to store security identification data and code to provide password protection, and

a low voltage differential signal (lvds) channel directly extending from the second interface controller, the lvds channel comprising at least two unidirectional, serial bit channels to convey data in opposite directions,

wherein the CPU is configured to couple to the console through the lvds channel, and

wherein the first interface controller and the second interface controller are configured to convey data between the mass storage device and the console.

39. The system of claim 38, wherein the mass storage device is directly coupled to the CPU.

40. The system of claim 38, wherein the first interface controller is configured to couple to the second interface controller through the lvds channel.

41. The system of claim 40, wherein the second interface controller is configured to output a serial bit stream that is conveyed over the lvds channel.

42. The system of claim 41, wherein the serial bit stream comprises address and data bits of PCI bus transaction.

43. The system of claim 42, wherein the computer module further comprises an enclosure with a connector on one side, the connector is coupled to the lvds channel to convey the serial bit stream of PCI bus transaction, and the computer module is configured to couple to the console through the connector.

44. The system of claim 41, wherein the serial bit stream comprises information of Universal serial Bus protocol.

45. The system of claim 38, wherein the computer module is configured to couple to the console as a “plug and play” operation.