Switching device having a non-linear element

Abstract

Method for a memory including a first, second, third and fourth cells include applying a read, program, or erase voltage, the first and second cells coupled to a first top interconnect, the third and fourth cells coupled to a second top interconnect, the first and third cells coupled to a first bottom interconnect, the second and fourth cells are to a second bottom interconnect, each cell includes a switching material overlying a non-linear element (NLE), the resistive switching material is associated with a first conductive threshold voltage, the NLE is associated with a lower, second conductive threshold voltage, comprising applying the read voltage between the first top and the first bottom electrode to switch the NLE of the first cell to conductive, while the NLEs of the second, third, and the fourth cells remain non-conductive, and detecting a read current across the first cell in response to the read voltage.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application

The value for the program voltage of the combined device can be expressed as:
VPROGRAMC≃small{large((RMOFF+RNOFF)/RNOFF)VTH1,VPROGRAM),large(VTH1,((RMOFF+RNOFF)/RMOFF)VPROGRAM)}
Where “small” indicates the smaller of two values in a set, and “large” indicates the larger of two values in a set. In most embodiments, the V_PROGRAM is significantly higher than V_TH1, and V_PROGRAMC is thus similar to V_PROGRAM.

FIG. 6C shows the result of a negative voltage sweep of the same switch in an OFF state. Because it is already in the OFF state, a negative voltage does not cause an erase operation, and the cell remains in a high resistance OFF state.

FIGS. 6D and 6E show I-V relationships of a combined device (e.g. memory cell 500) where the memory cell is initially in a low-resistance ON state. FIG. 6D shows a read operation, where the read voltage must be greater than threshold voltage V_THC1 to return an accurate read value. As the read voltage drops below the hold voltage V_HOLDC1, the resistance in the cell increases substantially. The threshold voltage of the combined device is related to the threshold voltage of the NLE through the following equation:
VTHC1=((RMON+RNOFF)/RNOFF)VTH1≃VTH1
Thus, the read threshold voltage of the combined device is approximately the same as the threshold voltage of the NLE, or V_THC1≅V_TH1.

Similarly, as seen in FIG. 6E, an erase operation must overcome a second threshold value V_THC2 to allow current to start flowing through the cell, and the switch is changed to a high-resistance OFF state at voltage V_ERASEC Like the positive threshold voltage, the negative threshold voltage of the combined device is about the same as the negative threshold voltage of the NILE. The value of the erase voltage V_ERASEC in a combined device can be expressed as:
VERASEC≃large((RMON+RNON)/RMON)VERASE,VTH2)
The relationship between the negative threshold voltages of a discrete and combined device can be expressed as:
VTHC2=((RMON+RNOFF)/RNOFF)VTH2≃VTH2.
So that in most embodiments, V_THC2≅V_TH2.

Various embodiments of a digital NLE can be made of many different materials. For example, a digital NLE can be a threshold device such as a film that experiences a field-driven metal-insulating (Mott) transition. Such materials are known in the art, and include VO₂ and doped semiconductors. Other threshold devices include material that experiences resistance switching due to electronic mechanisms observed in metal oxides and other amorphous films, or other volatile resistive switching devices such as devices based on anion or cation motion in oxides, oxide heterostructures, or amorphous films. A digital NLE can also be in the form of a breakdown element exhibiting soft breakdown behavior such as SiO₂, HfO₂, and other dielectrics. Examples of such breakdown elements are described in further detail by application Ser. No. 12/826,653, filed on Jun. 29, 2010, which is entitled “Rectification Element for Resistive Switching for Non-volatile Memory Device and Method,” and is incorporated by reference in its entirety. In other embodiments, the NLE may be a solid electrolyte material. The solid electrolyte material can include be chalcogenide based such as GexSy, GexSey, SbxTey, AgxSey, and CuxSy, or can be metal oxide based such as WOx, TiOx, AlOx, HfOx, CuOx, and TaOx, where 0<x<appropriate stoichiometric value (e.g. 2, 3, etc.) (e.g. GeS, GeSe, WO3, or SbTe, and the like).

As is known in the art, the precise values of threshold, hold, program and erase can be adjusted for different embodiments by changing the form of and materials used for the NLE and the memory cell. In various embodiments the threshold voltage for the NLE can be about the same as the hold voltage, the program voltage, or both. In other embodiments the threshold voltage for the NLE can exceed the program and erase voltages of a resistive switching device.

An analog NLE differs from a digital NLE in that its I-V relationship is characterized by a more gradual transition when current starts to flow through the element. As shown in FIG. 7A, which illustrates the response of an analog NLE to a voltage sweep, the current transition follows an exponential-like curve. The transition or threshold is therefore less abrupt than a digital NLE. Threshold voltage values where substantial current starts to flow through an analog NLE are designated as V_A and V_B for positive and negative bias values, respectively. Another significant difference between an analog and digital NLE is that an analog NLE does not experience the hysteretic hold voltage characteristic of a digital NLE.

FIGS. 7B to 7E show I-V characteristics of a combined device with an analog NLE. As shown in FIG. 7B, when a program voltage V_PROGRAMC is applied to a combined device where the switch is initially in an OFF state, the switch changes to a low resistance ON state. The V_PROGRAMC is approximately the sum of the V_A of the NLE and the V_PROGRAM of the switch as shown in FIG. 2, or V_PROGRAMC≈V_A+V_PROGRAM. As a result, the programming voltage of a combined device with an analog NLE is typically higher than the programming voltage of a switching element alone.

Turning now to FIG. 7C, a negative voltage sweep of a combined device in an OFF state is shown. Because the switch is already in an OFF state, the negative voltage does not induce a state change, and the switch remains in a high resistance state.

FIG. 7D shows the result of a read operation in a combined switch that is in an ON state. In the present embodiment, V_AC<V_READ<V_PROGRAMC. Because the switch is already in a low-resistance ON state, current flow above the threshold voltage V_AC is characterized by low resistance. Circuitry can detect the current flow, resulting in a positive read result. The value tier V_A is not affected by the switching apparatus in most embodiments, so typically V_AC≈V_A.

FIG. 7E shows an I-V curve for an erase operation in a combined device. To change the switch from the ON state to the OFF state, a voltage of V_ERASEC is applied to the combined device, thereby increasing the resistance of the switch. The voltage required to complete an erase operation in a combined device is normally the sum of the erase value of the discrete switch and the threshold value of the analog NLE, or V_ERASEC≈V_ERASE+V_B.

An analog NLE can be any element that exhibits the above described behavior. Examples of suitable materials include a punch-through diode, a Zener diode, an impact ionization (or avalanche) element, and a tunneling element such as a tunneling barrier layer. Such elements can be fabricated using standard fabrication techniques.

In most embodiments, |V_A, V_B|<|V_PROGRAM, V_ERASE|. As is known in the art, the precise threshold values of V_A, V_B, program, and erase can be adjusted for different embodiments by changing the form of and materials used for the NLE and the memory cell. In various embodiments the threshold voltage for the NLE can be about the same as the program voltage. In other embodiments the threshold voltage can exceed the program and erase voltages.

In other embodiments, a resistive switching cell may be configured to retain multiple resistive states. That is, rather than being configured to have binary states of ON and OFF, a cell can retain a plurality of resistance states. An array of such switches has the same limitations regarding leakage current, and would similarly benefit from the inclusion of an NLE.

FIGS. 8A-B illustrate examples according to various embodiments of the present invention. In various embodiments of the present invention, as discussed in FIG. 4, when a program (or read or erase) voltage is applied to a target cell 408, e.g. across second top electrode 418 and second bottom electrode 420, a sneak path 416 may allow a sneak path current to flow through cells 402, 404 and 406. To reduce this, a non-linear element, described above (e.g. NLE 504 in FIG. 5), was incorporated in each memory cell. The characteristics of an example NLE was illustrated in FIG. 6A. More particularly, when a voltage across the NLE exceeded VTH1 the resistance for the NLE switched from a relatively non-conductive state to a relatively conductive state. Accordingly, in an example, to program target cell 408, a program voltage would be applied to target cell 408 that would exceed VTH1 and exceed the programming voltage of target cell 408 (VProgram, FIG. 8A). In another example, to read target cell 408, a read (or program) voltage would be applied to target cell 408 that would exceed VTH1, but would be less than the programming voltage of target cell 408 (VProgram, FIG. 8A).

In an example described in co-pending application Ser. No. 13/290,024, filed Nov. 4, 2011, incorporated by reference above, the read voltage to the target cell was limited to be no greater than three times the threshold voltage of the nonlinear element. This three times number assumed that unselected top electrodes and unselected bottom electrodes in the memory array were allowed to float. By way of explanation, using the numbering of FIG. 4 above, in FIG. 8B, the read voltage would not only be applied across target cell 408, but also across sneak path 416 through cells 402, 404 and 406. In such a configuration, if the read (or program) voltage exceeded three times the voltage threshold (e.g. 3×VTH1) of the non-linear element, the voltage across non-linear element of 402, for example, would also exceed VTH1. Accordingly, the NLE of 402 would switch to a relatively-conductive state, and significant current could flow through the sneak path 416. It was recognized in the above incorporated patent application, that to reduce sneak path current, unselected cells, e.g. 402, 404 and 406 had to have voltages applied that were lower than the threshold voltage (e.g. VTH1) of the non-linear elements. For example, when the read (or program) voltage (V408) is applied across target cell 408, the resultant relationships should be met: voltage across cell(s) V402<VTH1, voltage across cell(s) V404<VTH1, and voltage across cell(s) 406<VVTH1. Additionally, the voltages across these unselected cells should be greater than VTH2 (FIG. 8A). By observing such conditions, it is understood that NLEs of unselected cells (along sneak paths) should have voltages across hem such that they remained non-conductive, see suppressed region 800 in FIG. 8A.

In various embodiments of the present invention, in the example of FIG. 4, during a read operation (for example), when the read voltage Vread is applied to target cell 408, the voltage Vread (e.g. VTH1<Vread (V408)<Vprogram, e.g. Vread=2 volts) is applied to second top electrode 418 and ground (e.g. Vg, e.g. Vg=0 volts) is applied to the second bottom electrode 420. In the case of a program operation V408>Vprogram. To reduce power consumption/requirements of the memory, the inventors have recognized that it is advantageous to set unselected bit lines (e.g. top electrodes/conductors) and unselected word lines (e.g. bottom conductors/electrodes) to voltages other than floating during a read operation. The specific voltages may vary, and are generally guided by the following concepts.

For a read (or program or erase) operation, for memory cells, e.g. memory cells 402, that share second top electrode 418 (e.g. selected bit line), the difference (V402) between the voltage across second top electrode 418 (VSBL) and unselected word lines, (e.g. first bottom electrode 412) (VUSWL) should be less than the voltage threshold of the NLE of memory cells such as memory cell 402. In variable format: VSBL−VUSWL<VTH1 or V402<VTH1 (FIG. 8A). This condition would inhibit the NLE memory cells such as memory cell 402 from entering into relatively non-conductive states. It should be noted that, depending upon the polarity of V402, to inhibit the NLE of memory cells, such as memory cell 402 from become relatively non-conductive in a reverse-bias condition, the relationship maybe VTH2<V402<VTH1. This was graphically illustrated by the flat region in FIG. 6D (0 to VTHC1), and the flat region in FIG. 6E (VTHC2 to 0), illustrated together in region 800 in FIG. 8A. These restrictions are desirable also in program or erase operations upon memory cell 408. In other memory configurations, these specific relationships and polarities may be changed.

For a read (or program or erase) operation, for memory cells, e.g. memory cells 406, that share second bottom electrode 420 (e.g. selected word line), the difference V406 between the voltage across unselected bit lines (e.g. first top electrode 410) (VUSBL) and second bottom electrode 420 (e.g. selected word line) (VSWL) should be less than the voltage threshold of the NLE of memory cells such as memory cell 406. In variable format: VUSBL−VSWL<VTH1 V406<VTH1. This condition would inhibit the NLE of memory cells such as memory cell 406 from entering into relatively non-conductive states. It should be noted that, depending upon the polarity of V406, to inhibit the NLE of memory cells, such as memory cell 406 from become relatively non-conductive in a reverse-bias, the relationship maybe VTH2<V406<VTH1. This was graphically illustrated by the flat region in FIG. 6D (0 to VTHC1), and the flat region in FIG. 6E (VTHC2 to 0), illustrated together in region 800 in FIG. 8A. These restrictions are desirable also in program or erase operations upon memory cells 404. In various embodiments, VTH1 and |VTH2| may be different, or similar. In other memory configurations, these specific relationships and polarities may be changed.

For a read (or program or erase) operation, for memory cells, e.g. memory cells 404, that share unselected word lines (e.g. first bottom electrode 412), the difference (V404) between the voltage across unselected bit lines (e.g. first top electrode 410) (VUSBL) and unselected word lines (e.g. first bottom electrode 412) (VUSWL) should be less than the voltage threshold of the NLE of memory cells such as memory cells 404. In variable format: VUSBL−VUSWL<VTH1 or V404<VTH1. This condition would inhibit the NLE of memory cell 404 from entering into a relatively non-conductive state. It should be noted that depending upon the polarity of V404, to inhibit the NLE of memory cells, such as memory cell 404 from become relatively non-conductive in a reverse-bias, the relationship maybe VTH2<V404<VTH1. This was graphically illustrated by the flat region in FIG. 6D (0 to VTHC1), and the flat region in FIG. 6E (VTHC2 to 0), illustrated together in region 800 in FIG. 8A. These restrictions are desirable also in program or erase operations upon memory cells 404. In other memory configurations, these specific relationships and polarities may be changed.

FIGS. 8A-B illustrate an example according to various embodiments of the present invention. In one example of the above, the programming voltage Vprogram=2 volts, the positive threshold voltage (VTH1) of the NLE=1 volt, and the negative threshold voltage (VTH2) of the NLE=−2 volts. In such a configuration, to perform a program operation, the selected word line (e.g. second bottom electrode 420) is grounded (VSWL=0 volts), and selected bit line (e.g. second top electrode 418) (VSBL) is greater than the positive threshold voltage (e.g. VTH1 (1 volt)<VSBL, Vprogram (2 volts)). Thus, Vprogram=V408. Additionally, the unselected word lines (e.g. first bottom electrode 412) are set to about 1.5 volts (VUSWL=1.5 volts), accordingly, the voltage across memory cells such as memory cells 402 are less than the NLE switching voltage (e.g. VTH2 (˜2 volts)<V402 (2 volts−1.5 volts=0.5 volts)<VTH1 (1 volts). Further, the unselected bit lines (e.g. first top electrode 410) (VUSBL) are set to about 0.5 volts, accordingly, the voltage across memory cells such as memory cells 406 are thus less than the NLE switching voltage (e.g. VTH2 (−2 volts)<V406 (0.5 volts−0 volts=0.5 volts)<VTH1 (1 volts). Still further, from above the unselected bit lines (e.g. first top electrode 410) are set to about 0.5 volts (VUSBL=0.5 volts), and the unselected word lines (e.g. first bottom electrode 412.) (VUSWL) are set to about 1.5 volts (VUSWL=1.5 volts). In such a configuration, because the bottom electrodes (e.g. 412) have a higher voltage than the top electrodes (e.g. 410), memory cells, such as memory cells 404 are in a reverse bias voltage region. Accordingly, the voltage across memory cells such as memory cell 404 are less than the NLE switching voltage VTH1, but also need to be greater than VTH2: (e.g. VTH2 (−2 volts)<V404 (0.5 volts−1.5 volts=−1.0 volts)<VTH1 (1 volts). As mentioned above, these restrictions are also desirable in write and erase operations. For example in a read case VTH1<Vread (V408)<Vprogram; and in an erase case Verase (V408)<VTH2.

In various embodiments, based upon the voltages V408, V402, V406, V404, and the like, the current requirements of memory cells may be computed during read, program, or erase operations. For example, power consumption for memory cells such as memory cells 402 (along the selected bit line second top electrode 418) is the number of cells times the current across memory cells (V402 (e.g. 0.5 volts)/resistance of NLE in relatively non-conductive state); plus power consumption for memory cells such as memory cells 406 (along unselected bit lines, first top electrode 410) is the number of cells times the current across memory cells (V406 (e.g. 0.5 volts)/resistance of NLE in relatively non-conductive state); plus power consumption for memory cells such as memory cells 404 (along unselected bit lines, first top electrode 410, and along unselected word lines, first bottom electrode 412) is the number of cells times the current across the memory cells (V404 (e.g. −1 volt)/resistance of NLE in relatively non-conductive state). In some embodiments, setting of the bias voltages of unselected bit lines 410 (VUSBL) and unselected word lines may 412 (VUSWL) be made considering the power consumption described above.

In one example, using a large array (e.g. 100×100) of memory cells, if the voltage of the unselected bit lines (e.g. first top electrode 410) (VUSBL) and the unselected word lines (e.g. first bottom electrode 412) (VUSWL) are substantially the same the voltages, V404 is small (e.g. about 0). Accordingly, the power consumption of these memory cells (99 cells×99 cells=9801 cells) is small (e.g. about 0), and power consumed/required is computed, consumed, mainly from the memory cells along the selected bit line 418 (99 cells along the second top electrode 418) and from the memory cells along the selected word line 420 (99 cells along the second bottom electrode 420). In one example of this VSBL=4V, VSWL=0V, VUSBL=2V, VUSWL=2V.

Although certain of the above passages have been described with respect to a read operation, it should be understood that the above also apply to other operations, such as programming operations and erase operations. In each of these situations, embodiments of the present invention incorporating NLE elements within a memory cell help to reduce sneak paths/currents through unselected memory cells. More particularly, for memory cells 402, 404 and 406 along sneak path 416, the voltages across these cells should be within a NLE non-conductive (suppressed) region 800, illustrated in FIG. 8A, to reduce sneak path current. This is in comparison with the graph illustrated in FIG. 2, for embodiments without NLE-type elements.

In other embodiments, NLEs with different threshold voltages may be used, resistive switching material having different program and erase voltages may be used, different voltages may be applied to bias unselected word lines and/or unselected bit lines, different polarity materials may be used, and the like. Still other embodiments may be applied to unipolar-type memory cells.

In light of the present patent disclosure, one of ordinary skill in the art will recognize that in other embodiments, the voltages for selected bit lines, unselected bit lines, selected word lines, unselected word lines, NLE threshold voltages, read voltages, and the like may vary from those illustrated above, depending upon specific engineering requirements, e.g. power consumption, performance, and the like

The examples and embodiments described herein are for illustrative purposes only and are not intended to be limiting. Various modifications or alternatives in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.

Claims

1. Method for operating a memory comprising:

applying a read voltage to the memory, wherein the memory comprising a plurality of cells including at least a first cell, a second cell, a third cell, and a fourth cell,

wherein the first cell and the second cell are coupled to a first top electrode,

wherein the third cell and the fourth cell are coupled to a second top electrode,

wherein the first cell and the third cell are coupled to a first bottom electrode,

wherein the second cell and the fourth cell are coupled to a second bottom electrode,

wherein each cell of the plurality of cells comprises a resistive switching material stack comprising a resistive switching material overlying a non-linear switching element material,

wherein the resistive switching material is characterized by a first voltage associated with switching from a non-conductive state to a conductive state,

wherein the non-linear switching element material is characterized by a second voltage associated with switching from a non-conductive state to a conductive state,

wherein the second voltage is less than the first voltage,

wherein the read voltage is between the first voltage and the second voltage, and

wherein applying the read voltage to the memory comprises applying the read voltage to the first top electrode while grounding the first bottom electrode to thereby cause non-linear switching element material of the first cell to be in the conductive state, while maintaining non-linear switching element material of the second cell, the third cell, and the fourth cell to remain in the non-conductive state; and

detecting a read current across the first cell in response to the read voltage.;

wherein the resistive switching material is characterized by a third voltage associated with switching from the conductive state to the non-conductive state;

wherein the non-linear switching element material is characterized by a fourth voltage associated with switching from the non-conductive state to the conductive state; and

wherein the third voltage is less than the fourth voltage.

2. The method of claim 1 wherein a resistance of the non-conductive state is related to a resistance of the conductive state in a range of ratios selected from a group consisting of: about 100 to about 500 times greater, about 500 to about 1000 times greater, about 1000 times to about 10,000 times greater.

3. The method of claim 1 wherein while applying the read voltage to the first top electrode while grounding the first bottom electrode, a voltage across the second cell is maintained at less than the second voltage.

4. The method of claim 1

wherein the resistive switching material is characterized by a third voltage associated with switching from the conductive state to the non-conductive state;

wherein the non-linear switching element material is characterized by a fourth voltage associated with switching from the non-conductive state to the conductive state; and

wherein the third voltage is less than the fourth voltage.

5. The method of claim 4 1 wherein while applying the read voltage to the first top electrode while grounding the first bottom electrode, a voltage across the fourth cell is maintained at greater than the fourth voltage to thereby maintain the non-linear switching element material of the third cell in the non-conductive state.

6. The method of claim 4 1 wherein while applying the read voltage to the first top electrode while grounding the first bottom electrode, the method further comprises applying a fifth voltage between ground and the read voltage to the second bottom electrode.

7. The method of claim 6 wherein while applying the read voltage to the first top electrode while grounding the first bottom electrode, the method further comprises applying a sixth voltage between ground and the read voltage to the second top electrode.

8. The method of claim 7 wherein a difference between the sixth voltage and the fifth voltage is greater than the fourth voltage.

9. The method of claim 1 further comprising:

applying a write voltage to the memory, wherein the write voltage exceeds the first voltage, wherein applying the write voltage to the memory comprises applying the write voltage to the first top electrode while grounding the first bottom electrode to thereby cause the resistive switching material of the first cell to be in the conductive state.

10. The method of claim 9 wherein applying the write voltage to the first top electrode comprises applying the write voltage to the first top electrode while grounding the first bottom electrode to thereby cause the non-linear switching element material of the first cell to switch from the non-conductive state to the conductive state.

11. A memory operated according to the method described in claim 1.

12. A memory comprising:

a plurality of cells including at least a first cell, a second cell, a third cell, and a fourth cell, wherein each cell of the plurality of cells comprises a resistive switching material stack comprising a resistive switching material overlying a non-linear switching element material, wherein the resistive switching material is characterized by a first voltage associated with switching from a non-conductive state to a conductive state, wherein the non-linear switching element material is characterized by a second voltage associated with switching from a non-conductive state to a conductive state, wherein a second voltage is less than the first voltage;

a plurality of top electrodes including a first top electrode and a second top electrode, wherein the first cell and the second cell are coupled to the first top electrode, and wherein the third cell and the fourth cell are coupled to the second top electrode;

a plurality of bottom electrodes including a first bottom electrode and a second bottom electrode, wherein the first cell and the third cell are coupled to the first bottom electrode, and wherein the second cell and the fourth cell are coupled to the second bottom electrode, wherein a read current path is associated with the first cell, wherein non-read current paths are associated with the second cell, the third cell, and the fourth cell, wherein the non-linear switching element material of the first cell is configured to reduce resistance of the read current path, and wherein the non-linear switching element material of the second cell, the third cell, and the fourth cell are configured to increase resistance of the non-read current; and

a voltage source coupled to the plurality of top electrodes and to the plurality of bottom electrodes, wherein the voltage source is configured to provide a plurality of voltages to the plurality of top electrodes and to the plurality of bottom electrodes.;

wherein the resistive switching material is characterized by a third voltage associated with switching from the conductive state to the non-conductive state;

wherein the non-linear switching element material is characterized by a fourth voltage associated with switching from the non-conductive state to the conductive state; and

wherein the third voltage is less than the fourth voltage.

13. The memory of claim 12

wherein the non-linear switching element material of the first cell is configured to be in the conductive state dependent upon a read voltage that is greater than the second voltage but less than the first voltage, that is applied to the first top electrode while grounding the first bottom electrode; and

wherein the voltage source is configured to provide the read voltage.

14. The memory of claim 12

wherein the non-linear switching element material of the second cell is configured to be in the non-conductive state dependent upon a read voltage that is greater than the second voltage but less than the first voltage, is applied to the first top electrode while grounding the first bottom electrode; and

wherein the voltage source is configured to provide the read voltage.

15. The memory of claim 14 wherein when the read voltage is applied to the first top electrode while grounding the first bottom electrode, a voltage greater than ground is applied to the second bottom electrode such that a voltage across the second cell is less than the second voltage.

16. The memory of claim 12 wherein the resistive switching material is selected from a group consisting of: an amorphous silicon material, a silicon sub-oxide, a silicon germanium sub-oxide.

17. The memory of claim 12 wherein each of the plurality of bottom electrodes comprises a metal or a conductive silicon material selected from a group consisting of: a doped polysilicon, and a doped silicon germanium material.

18. The memory of claim 12

wherein the resistive switching material is characterized by a third voltage associated with switching from the conductive state to the non-conductive state;

wherein the non-linear switching element material is characterized by a fourth voltage associated with switching from the non-conductive state to the conductive state; and

wherein the third voltage is less than the fourth voltage.

19. The memory of claim 12

wherein the non-linear switching element material of the fourth cell is configured to be in the non-conductive state dependent upon a read voltage that is greater than the second voltage but less than the first voltage, that is applied to the first top electrode while grounding the first bottom electrode; and

wherein a voltage difference greater than the fourth voltage is applied to the fourth cell.

20. The memory of claim 12

wherein the voltage source is configured to provide a read voltage to the first top electrode, wherein the voltage source is configured to provide a fifth voltage to the second bottom electrode and a sixth voltage to the second top electrode, wherein a voltage difference between the second top electrode and the second bottom electrode is greater than the fourth voltage.

21. The memory of claim 12 wherein a ratio between the resistance of the first cell compared to a resistance of the second cell is greater than 1:1000.

22. The memory cell of claim 12 wherein the non-linear switching material is selected from a group consisting of: a solid electrolyte material and a metal sub-oxide.

23. The memory cell of claim 12 wherein the non-linear switching material is bi-polar.

24. The memory cell of claim 12 wherein the non-linear switching material consists of multiple layers of materials.

25. A method for operating a memory comprising:

applying a program voltage to the memory, wherein the memory comprising a plurality of cells including at least a first cell, a second cell, a third cell, and a fourth cell,

wherein the first cell and the second cell are coupled to a first top electrode,

wherein the third cell and the fourth cell are coupled to a second top electrode,

wherein the first cell and the third cell are coupled to a first bottom electrode,

wherein the second cell and the fourth cell are coupled to a second bottom electrode,

wherein each cell of the plurality of cells comprises a resistive switching material stack comprising a resistive switching material having crystal defect regions and a non-linear switching element material,

wherein each cell is characterized by a first first-polarity voltage associated with the resistive switching material switching from a non-conductive state to a conductive state and a first second-polarity voltage associated with the resistive switching material switching from the conductive state to the non-conductive state,

wherein each cell is characterized by a second first-polarity voltage and a second second-polarity voltage associated with the non-linear switching element material switching from a second non-conductive state to a second conductive state,

wherein the second first-polarity voltage is less than the first first-polarity voltage,

wherein the first second-polarity voltage is less than the second second-polarity voltage,

wherein the program voltage is greater than or equal to the first first-polarity voltage, and

wherein applying the program voltage to the memory comprises applying the program voltage to the second top electrode;

grounding the second bottom electrode;

applying a first bias to the first top electrode and applying a second bias to the first bottom electrode;

causing a non-linear switching element material of the fourth cell to enter the conductive state and causing a resistive switching material of the fourth cell to enter the conductive state,

maintaining non-linear switching element materials of the first cell, the second cell, and the third cell in the non-conductive state in response to the applying the program voltage, grounding the second bottom electrode, the applying the first bias and the applying the second bias; and

removing the program voltage from the second top electrode, whereby the non-linear switching element material of the fourth cell returns to the non-conductive state, and wherein the resistive switching material of the fourth cell remains in the conductive state.

26. The method of claim 25

wherein applying the program voltage to the second top electrode while grounding the second bottom electrode causes metal particles from the second top electrode to diffuse into crystal defect regions of the resistive switching material of the fourth cell; and

wherein after removing the program voltage from the second top electrode, the metal particles from the second top electrode remain trapped in the crystal defect regions of the resistive switching material of the fourth cell.

27. The method of claim 25 wherein while applying the program voltage to the second top electrode while grounding the second bottom electrode, a voltage across the second cell is maintained at less than the second first-polarity voltage.

28. The method of claim 25

wherein the first and second first-polarity voltages are positive; and

wherein the first and second second-polarity voltage are negative.

29. The method of claim 28 wherein

applying the first bias to the first top electrode comprises applying a first bias voltage less than the second first-polarity voltage to the first top electrode; and

wherein a voltage across the second cell in response to the applying the first bias voltage is less than the second first-polarity voltage.

30. The method of claim 29

wherein applying the second bias to the first bottom electrode comprises applying a second bias voltage to the first bottom electrode;

wherein a voltage difference between the program voltage and the second bias voltage is less than the second first-polarity voltage; and

wherein a voltage across the third cell is less than the second first-polarity voltage.

31. The method of claim 30

wherein a voltage across the first cell comprises a third second-polarity voltage; and

wherein the second second-polarity voltage is less than the third second-polarity voltage.

32. The method of claim 25 wherein a resistance ratio between the second conductive state to the second non-conductive state of the non-linear switching element material is within a range of about 1,000 to about 10,000.

33. The method of claim 25 further comprising:

applying an erase voltage to the second top electrode;

further grounding the second bottom electrode;

further biasing the first top electrode;

further biasing the first bottom electrode to thereby cause the non-linear switching element material of the fourth cell to enter the conductive state and cause the resistive switching material of the fourth cell to enter the non-conductive state, while maintaining non-linear switching element materials of the first cell, the second cell, and the third cell in the non-conductive state; and

removing the erase voltage from the second top electrode, whereby the non-linear switching element material of the fourth cell returns to the non-conductive state, and wherein the resistive switching material of the fourth cell remains in the non-conductive state.

34. The method of claim 33, wherein:

the further biasing the first top electrode comprises applying a first bias voltage less than the second first-polarity voltage to the first top electrode; and

a voltage across the second cell in response to the applying the first bias voltage is greater than the second second-polarity voltage and less than the second first-polarity voltage.