A titanium film is formed in a contact hole defined in a silicon substrate. The titanium film is transformed into a titanium silicide film and a first titanium nitride film by high-temperature lamp anneal. Further, a second titanium nitride film is stacked on the first titanium nitride film. Conditions are applied under which the titanium nitride films are formed into a granular crystal of primarily a (200) orientation. Therefore, barrier characteristics of the titanium nitride films to silicon atoms is not compromised even in the case of a subsequent high-temperature thermal treatment.

Patent
   5654235
Priority
Aug 18 1994
Filed
Jun 22 1995
Issued
Aug 05 1997
Expiry
Jun 22 2015
Assg.orig
Entity
Large
45
18
all paid
10. A method of manufacturing a semiconductor device having an impurity diffusion layer formed on a silicon substrate and an ohmic contact including a metal interconnect, said ohmic contact being formed on the silicon substrate, said method comprising the steps of:
defining a contact hole in an interlayer insulating film provided on the impurity diffusion layer;
then forming a first refractory metal layer in the contact hole;
then applying a thermal treatment by lamp anneal for transforming a surface on the refractory metal layer into a first refractory metal nitride layer and orienting the first refractory metal nitride layer primarily in the form of a granular crystal; and
then forming a second refractory metal nitride layer primarily in the form of a granular crystal on the first refractory metal nitride layer.
1. A method of manufacturing a semiconductor device having an impurity diffusion layer formed on a silicon substrate and an ohmic contact including a metal interconnect, said ohmic contact being formed on the silicon substrate, said method comprising the steps of:
defining a contact hole in an interlayer insulating film provided on the impurity diffusion layer;
then forming a first titanium layer in the contact hole;
then applying a thermal treatment by lamp anneal for transforming a surface on the titanium layer into a first titanium nitride layer and for orienting the first titanium nitride layer primarily in the form of a granular crystal with a (200) orientation; and
then forming a second titanium nitride layer oriented primarily in the form of a granular crystal with a (200) orientation on the first titanium nitride layer.
5. A method of manufacturing a semiconductor device having an impurity diffusion layer formed on a silicon substrate and an ohmic contact including a refractory metal interconnect, said ohmic contact being formed on the silicon substrate, said method comprising the steps of:
defining a contact hole in an interlayer insulating film provided on the impurity diffusion layer;
then forming a first titanium layer in the contact hole;
then applying a first thermal treatment by lamp anneal for transforming a surface on the titanium layer into a first titanium nitride layer and for orienting the first titanium nitride layer primarily in the form of a granular crystal with a (200) orientation;
then forming a second titanium nitride layer oriented primarily in the form of a granular crystal with a (200) orientation on the first titanium nitride layer;
then forming the refractory metal interconnect on the second titanium nitride layer; and
applying a second thermal treatment.
2. The method as claimed in claim 1, wherein the second titanium nitride layer has a thickness ranging from 30 nm to 100 nm.
3. The method as claimed in claim 1, wherein the metal interconnect is a refractory metal interconnected.
4. The method as claimed as claim 1, wherein the lamp anneal is carried out in an ambient of nitrogen or ammonia at a temperature ranging from 800°C to 900°C
6. The method as claimed in claim 5, wherein the second titanium nitride layer has a film thickness ranging from 30 nm to 100 nm.
7. The method as claimed in claim 5, wherein the refractory metal interconnect is a tungsten interconnect.
8. The method as claimed in claim 5, wherein the lamp anneal is carried out in an ambient of nitrogen or ammonia at a temperature ranging from 800°C to 900°C
9. The method as claimed in claim 5, wherein the second thermal treatment is performed at a temperature ranging from 850°C to 950° C.

1. Field of the Invention

This invention relates to a contact structure suitable for use in a semiconductor device and a method of manufacturing the contact structure, and particularly to a structure for electrically connecting metal interconnects to a contact substrate using a barrier metal and a method of manufacturing the structure.

2. Description of the Related Art

Aluminum or an aluminum alloy is principally used in a contact as a material for forming a metal interconnect ohmic-connected to an impurity diffusion region formed on a silicon substrate. In this case, a single-layer interconnect composed of aluminum or the aluminum alloy reacts with silicon in a contact diffusion region by a thermal treatment to produce alloy spikes or silicon nodules that cause an increase in contact resistance. Means such as a method of interposing a barrier metal film between a metal interconnect and an impurity diffusion region, etc. are used as countermeasures against such a problem. A titanium nitride is principally used as such a barrier metal film in view of barrier characteristics. However, the conventional titanium nitride is of a single-layer film and is utilized in crystal orientation of (111). A problem arises that a titanium nitride has weak resistance to a rapid or high-temperature thermal treatment as described in Japanese Patent Application Laid-Open No. 5-13368, for example.

With the foregoing in view, it is therefore an object of the present invention to prevent a leakage current from flowing in a contact using a barrier metal.

In order to achieve the above object, there is provided a semiconductor device having a contact structure wherein a plurality of titanium nitrides used as barrier metals are stacked on one another and crystals of the titanium nitrides are formed with granular crystals as principal, and a method of manufacturing the semiconductor device.

It is another object of the present invention to provide a contact using a barrier metal resistant to a high-temperature thermal treatment.

In order to achieve the object referred to above, there is provided a semiconductor device wherein a titanium nitride used as a barrier metal is crystallized with granular crystals as principal and reliability of a contact is prevented from impairment even if a high-temperature thermal treatment is effected on the contact, and a method of manufacturing the semiconductor device.

A high degree of reliability of the semiconductor device in which the barrier metal is employed in the contact, can be realized owing to the above construction.

While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:

FIG. 1 is a cross-sectional view showing a contact for describing a first embodiment of the present invention;

FIG. 2 is a view typically illustrating a titanium nitride oriented in the form of granular crystals;

FIG. 3 is a view typically showing a titanium nitride oriented in the form of columnar crystals;

FIG. 4 is a cross-sectional view depicting a contact for describing a second embodiment of the present invention;

FIG. 5 is a view illustrating the dependence of a glass flow temperature on a sheet resistance of a tungsten interconnect in the contact for describing the second embodiment shown in FIG. 4; and

FIG. 6 is a view showing the intensity of X-ray diffraction of a thermal-treated sample employed in the second embodiment of the present invention, which is obtained by stacking first and second titanium nitrides on a titanium silicide.

Preferred embodiments of the present invention will hereinafter be described with reference to the accompanying drawings. In this case, elements directly associated with the present invention will be described in detail.

First and second embodiments of the present invention will be described with reference to the accompanying drawings.

The first embodiment of the present invention will first be described.

FIG. 1 is a cross-sectional view of a contact showing the first embodiment of the present invention. In FIG. 1, a first interlayer insulating film 2 composed of a CVD oxide (SiO2), a phospho-silicate glass (PSG), etc. is deposited on a silicon substrate 1. Thereafter, the first interlayer insulating film 2 is patterned to form a first contact hole 9. Next, impurity diffusion is effected on the silicon substrate 1 with the first contact hole 9 defined therein to form an impurity diffusion layer 3. Further, a titanium film 4 having a thickness of 10 nm to 30 nm is deposited on the impurity diffusion layer 3 by sputtering. Next, rapid thermal anneal such as lamp anneal is effected on the titanium film 4 in an N2 ambient at a temperature in the range of 800°C to 900°C to thereby transform the titanium film 4 into a titanium silicide 5 having a thickness in the range of about 16 nm to 48 nm and a first titanium nitride 6 having a thickness of about 2 nm. Further, a second titanium nitride 7 having a thickness in the range of 30 nm to 100 nm is deposited on the titanium nitride 6 by reactive sputtering. Reactive sputtering conditions include 100% N2 gas, a gas pressure of 4 mm Torr and a power of 6KW. At this time, crystal orientation of the titanium nitride formed by reactive sputtering tends to take (200) as principal (this expression is intended to mean the same as "principally" or "primarily", as explained below in connection with FIG. 6), which has been reported in the article "Diffusion Barrier with Reactively Sputtered TiN Film for Thermally Stable Contact in Advanced VLSI" published in the Extended Abstract of the 20th (1989 International) Conference on Solid State Devices and Materials, Tokyo, 1988, pp. 569-572. Crystals of (200) as principal are of granular crystals. Further, patterning is performed on the resultant product and the second titanium nitride 7, the first titanium nitride 6 and the titanium film 4 are successively etched. Thereafter, an aluminum alloy 8 having a thickness range of about 300 nm to 700 nm is deposited on the second titanium nitride 7 by sputtering.

According to the present contact structure, since a plurality of titanium nitrides are stacked on one another and the titanium nitrides are oriented in the form of the granular crystals, a stable contact can be obtained which can provide a low resistance and less leakage current. This will be described later in detail in the paragraph of a second embodiment of the present invention. It is however considered that a lower titanium nitride becomes a film obtained by providing crystalline orientation for it with (200) as principal by lamp annealing using a temperature of 800°C or over and an upper titanium nitride also becomes a film obtained by providing more crystalline orientation for it with (200) as principal according to the lower titanium nitride. The leakage current is considered to have been reduced because grain boundaries considered to be closely connected with a silicon diffusion path are not broadened orientationally but at random intervals by forming the titanium nitrides in the form of the granular crystals typified by (200) as typically shown in FIG. 2 as compared with a structure shown in FIG. 3 illustrative of a conventional columnar crystal represented by (111), and silicon diffusion paths for causing a current to flow between the upper and lower titanium nitrides are hard to connect owing to a stack structure and suppress silicon diffusion into silicon substrate, thereby enabling prevention of the leakage current.

A second embodiment of the present invention will now be described.

FIG. 4 is a cross-sectional view of a contact showing the second embodiment of the present invention. In FIG. 4, a first interlayer insulating film 12 composed of a CVD oxide, a phosopho-silicate glass, etc. is deposited on a silicon substrate 11. Thereafter, the first interlayer insulating film 12 is patterned to form a first contact hole 19. Next, impurity diffusion is effected on the silicon substrate 11 with the first contact hole 19 defined-therein to form an impurity diffusion layer 13. Further, a titanium film 14 having a thickness range of 10 nm to 30 nm is deposited on the impurity diffusion layer 13 by sputtering.

Next, lamp anneal is effected on the titanium film 14 in an N2 ambient at a temperature of 800°C to 900°C to thereby transform the titanium film 14 into a titanium silicide 15 having a thickness in the range of about 16 nm to 48 nm and a first titanium nitride 16 having a thickness of about 2 nm. Further, a second titanium nitride 17 having a thickness in the range of 30 nm to 100 nm is deposited on the titanium nitride 16 by reactive sputtering. Furthermore, a tungsten 18 having a thickness in the range of 200 nm to 400 nm is deposited on the second titanium nitride 17 by CVD and patterning is effected on the tungsten 18 to successively etch the tungsten 18, the second titanium nitride 17, the first titanium nitride 16 and the titanium film 14.

Next, a second interlayer insulating film 20 such as a silicon oxide film, a phosopho-silicate glass or the like, is deposited on the first interlayer insulating film 12. A glass flow is made to the second interlayer insulating film 20 at a temperature of 850°C to 950°C, followed by patterning, thereby defining a second contact hole 21 in the second interlayer insulating film 20. Further, an aluminum alloy 22 having a thickness in the range of about 300 nm to 700 nm is deposited on the second interlayer insulating film 20 by sputtering.

FIG. 5 illustrates the dependence of glass flow temperature on sheet resistance of a tungsten interconnect in the contact shown in FIG. 4 for describing the second embodiment of the present invention. It is apparent from the drawing that even in the case of a high-temperature thermal treatment carried out at a temperature in the range of about 850° C. to 950°C, which could not be achieved by a conventional device or method, a substantial increase in the contact sheet resistance does not take place and barrier characteristics of the titanium nitrides are maintained.

This phenomenon has been referred to cursorily in the first embodiment but is considered to depend on the crystalline of each titanium nitride. Conventional titanium nitrides, which have been widely used at large, are of columnar crystals typically shown in FIG. 3 as mentioned above. Since the titanium nitrides are of the columnar crystals, stresses are concentrated on the titanium nitrides due to the completeness of crystalline formation at the time of the high-temperature thermal treatment and hence cracks can easily occur. Further, owing to columnar grain boundaries, atoms are brought to intergranular diffusion so as to become easy to pass through the titanium nitrides.

It is therefore considered in the conventional example that silicon atoms supplied from a silicon substrate pass through titanium nitrides and react With tungsten so as to become tungsten silicide, thereby causing an increase in the resistance of a contact.

FIG. 6 illustrates the intensity of X-ray diffraction of a glass-flowed sample employed in the second embodiment of the present invention, which is obtained by stacking first and second titanium nitrides on titanium silicide. As is apparent from the drawing, it can be understood that the orientation of the crystalline formation of the stacked titanium nitride is dependent upon a lamp annealing temperature of titanium for forming the first titanium nitride. In the case of lamp anneal carried out at a temperature of 700°C, the titanium nitride is crystal-oriented with (111) as principal, whereas the titanium nitride becomes a film obtained by firmly crystal-orienting the titanium nitride with (200) as principal in the case of lamp anneal carried out at a temperature of 800°C or more. It is inferable in the present embodiment that the first titanium nitride is crystal-oriented with (200) as principal by effecting lamp anneal on the titanium film at a high temperature of 800°C or higher, and the second titanium nitride is formed in a stack based on producing conditions under which it is considered that the first titanium nitride is easy to be crystal-oriented to the conventional (200) as a stacked crystal, thereby obtaining the crystal orientation of the titanium nitride to (200). According to the structure of the titanium nitrides crystal-oriented in granular form as in the case of (200), since the stresses are diffused upon thermal treatment even if the completeness of crystalline takes place, the cracks do not readily occur. It is believed that even if the diffusion of the grain boundaries takes place, the probability of causing the silicon atoms supplied from the silicon substrate to pass through the titanium nitrides is extremely low due to the grain boundaries defined in granular form. It is considered that owing to the above reasons, the leakage current flowing through the contact is less generated, the silicide does not react with the tungsten and the resistance of the contact is not increased.

While the present invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.

Matsumoto, Ryoichi, Kawazu, Yoshiyuki

Patent Priority Assignee Title
10424729, May 31 2007 OVONYX MEMORY TECHNOLOGY, INC. Resistive memory architectures with multiple memory cells per access device
10453747, Aug 28 2017 GLOBALFOUNDRIES U S INC Double barrier layer sets for contacts in semiconductor device
10797237, May 31 2007 Micron Technology, Inc. Resistive memory architectures with multiple memory cells per access device
11349072, May 31 2007 OVONYX MEMORY TECHNOLOGY, LLC Resistive memory architectures with multiple memory cells per access device
11688601, Nov 30 2020 International Business Machines Corporation Obtaining a clean nitride surface by annealing
11837468, Oct 26 2020 Samsung Display Co., Ltd.; Industry-Academic Cooperation Foundation, Yonsei University Stacked structure including semiconductor structure and method of manufacturing the same
5776831, Dec 27 1995 Bell Semiconductor, LLC Method of forming a high electromigration resistant metallization system
5895267, Jul 09 1997 Bell Semiconductor, LLC Method to obtain a low resistivity and conformity chemical vapor deposition titanium film
5911857, Jun 27 1996 Hyundai Electronics Industries Co., Ltd. Method for forming metal wiring of semiconductor devices
6054768, Oct 02 1997 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Metal fill by treatment of mobility layers
6057231, Oct 02 1997 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Method for improved metal fill by treatment of mobility layers
6093642, Sep 23 1998 Texas Instruments Incorporated Tungsten-nitride for contact barrier application
6100182, Jun 23 1997 Hyundai Electronics Industries, Co., Ltd. Method for forming metal interconnection of semiconductor device
6100185, Aug 14 1998 Micron Technology, Inc. Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line
6177338, Feb 08 1999 Taiwan Semiconductor Manufacturing Company Two step barrier process
6187673, Sep 03 1998 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Small grain size, conformal aluminum interconnects and method for their formation
6207557, Jul 22 1998 Samsung Electronics Co., Inc. Method of forming multilayer titanium nitride film by multiple step chemical vapor deposition process and method of manufacturing semiconductor device using the same
6225222, Dec 29 1995 United Microelectronics Corporation Diffusion barrier enhancement for sub-micron aluminum-silicon contacts
6242804, Oct 24 1996 Fujitsu Semiconductor Limited Fabrication process of a semiconductor device having a nitride film
6291342, Jul 22 1998 Samsung Electronics Co., Ltd. Methods of forming titanium nitride composite layers using composite gases having increasing TiCl4 to NH3 ratios
6297555, Jul 09 1997 Bell Semiconductor, LLC Method to obtain a low resistivity and conformity chemical vapor deposition titanium film
6365507, Mar 01 1999 CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC Method of forming integrated circuitry
6417101, Dec 28 1999 Hyundai Electronics Industries Co., Ltd. Method for manufacturing semiconductor memory device incorporating therein copacitor
6482735, Oct 02 1997 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Method for improved metal fill by treatment of mobility layers
6503824, Oct 12 2001 Promos Technologies Inc Forming conductive layers on insulators by physical vapor deposition
6524951, Mar 01 1999 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Method of forming a silicide interconnect over a silicon comprising substrate and method of forming a stack of refractory metal nitride over refractory metal silicide over silicon
6688584, May 16 2001 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Compound structure for reduced contact resistance
6774487, Sep 03 1998 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Small grain size, conformal aluminum interconnects and method for their formation
6780086, Oct 12 2001 Promos Technologies Inc Determining an endpoint in a polishing process
6812139, Oct 02 1997 Micron Technology, Inc. Method for metal fill by treatment of mobility layers
6946393, Sep 03 1998 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Small grain size, conformal aluminum interconnects and method for their formation
6951786, Mar 01 1999 Micron Technology, Inc. Method of forming a stack of refractory metal nitride over refractory metal silicide over silicon
6984874, Oct 02 1997 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Semiconductor device with metal fill by treatment of mobility layers including forming a refractory metal nitride using TMEDT
7037829, May 16 2001 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Compound structure for reduced contact resistance
7038318, May 16 2001 Micron Technology, Inc. Compound structure for reduced contact resistance
7109115, May 16 2001 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Methods of providing ohmic contact
7217661, Sep 03 1998 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Small grain size, conformal aluminum interconnects and method for their formation
7232753, Dec 31 2003 DONGBU ELECTRONICS CO , LTD Method of fabricating semiconductor device
7276795, Sep 03 1998 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Small grain size, conformal aluminum interconnects and method for their formation
7311946, May 02 2003 VERSUM MATERIALS US, LLC Methods for depositing metal films on diffusion barrier layers by CVD or ALD processes
7452810, Jun 21 2002 Samsung Electronics Co., Ltd. Method of forming a barrier layer of a semiconductor device
7545009, May 16 2001 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Word lines for memory cells
7560816, Sep 03 1998 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Small grain size, conformal aluminum interconnects and method for their formation
7737024, Sep 03 1998 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Small grain size, conformal aluminum interconnects and method for their formation
7985449, May 02 2003 VERSUM MATERIALS US, LLC Methods for depositing metal films onto diffusion barrier layers by CVD or ALD processes
Patent Priority Assignee Title
4937657, Aug 27 1987 Signetics Corporation Self-aligned metallization for semiconductor device and process using selectively deposited tungsten
5000818, Aug 14 1989 National Semiconductor Corporation Method of fabricating a high performance interconnect system for an integrated circuit
5049975, Mar 14 1989 Mitsubishi Denki Kabushiki Kaisha Multi-layered interconnection structure for a semiconductor device
5155063, Oct 09 1990 NEC Electronics Corporation Method of fabricating semiconductor device including an Al/TiN/Ti contact
5162262, Mar 14 1989 Mitsubishi Denki Kabushiki Kaisha Multi-layered interconnection structure for a semiconductor device and manufactured method thereof
5231055, Jan 13 1989 Texas Instruments Incorporated Method of forming composite interconnect system
5242860, Jul 24 1991 APPLIED MATERIALS, INC A CORP OF DLEAWARE Method for the formation of tin barrier layer with preferential (111) crystallographic orientation
5444018, May 31 1991 Texas Instruments Incorporated Metallization process for a semiconductor device
5455197, Jul 16 1993 Tokyo Electron Limited Control of the crystal orientation dependent properties of a film deposited on a semiconductor wafer
DE3743591A1,
EP480409A1,
JP2119129,
JP2235372,
JP4112529,
JP5036843,
JP513368,
JP6151815,
JP6204170,
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