A chip with beveled edges suitable for adhering onto a surface of a die pad by an adhesive material. The chip has an active surface and a corresponding back surface, wherein the active surface has beveled edges. The back surface of the chip is adhered onto the surface of the die pad by the adhesive material.
|
1. A package of a semiconductor device, the package comprising:
a carrier having a die pad and a plurality of leads; a chip, located on a surface of the die pad, wherein the chip has an active surface and a corresponding back surface that are connected to each other via a plurality of side surfaces, wherein the active surface has beveled edges; an adhesive material attaching the back surface of the chip to the surface of the die pad, wherein the adhesive material covers the whole back surface of the chip and the side surfaces of the chip, the beveled edges of the active surface preventing a coverage of the active surface by the adhesive material; a plurality of wires electrically connecting the leads of the carrier to the active surface of the chip; and a molding compound covering the chip, the wires and a portion of the leads.
6. A package of a semiconductor device, the package comprising:
a carrier having a die pad and a plurality of leads; a plurality of chips, each chip having an active surface and a corresponding back surface that are connected to each other via a plurality of side surfaces, and the active surface has beveled edges, wherein the chips are stacked on one another on the die pad in such a manner that the active surface of one chip faces the back surface of one chip adjacently stacked thereon; an adhesive material respectively attaching the chips to one another and to the die pad, wherein the adhesive material respectively covers the whole back surface and the side surfaces of the chips, the beveled edges preventing a coverage of the corresponding active surfaces by the adhesive material; a plurality of wires, electrically connecting the leads of the carrier to the respective active surfaces of the chips; and a molding compound, covering the chips, the wires and a portion of the leads.
2. The package of
3. The package of
7. The package of
8. The package of
|
This application claims the priority benefit of Taiwan application serial no. 90105525, filed on Mar. 9, 2001.
1. Field of Invention
The present invention relates generally to a semiconductor package. More particularly, the present invention relates to a package of a chip with beveled edges.
2. Description of the Related Art
In semiconductor packaging, an attaching process for chips is a necessary step in the packaging fabrication. The attaching process comprises attaching a chip onto a carrier. A conventional package comprises a die pad on the carrier, which can allow the chip to adhere onto the carrier by utilizing an adhesive material. The adhesive material is usually filled in between the chip and the carrier as well as the sides of the chip in order to ensure the adhesive bonding between the chip and the carrier.
However, the adhesive material 102 often exceeds the edges of the chip. Due to surface tension, the adhesive material 102 will flow along the sides 112 of the chip 104 to its top surface, such as an active surface 114, of the chip 104. As a result, the active surface of the chip is polluted by the adhesive material. With the development of the semiconductor package, the size of the chip has been decreasing. Because of the decrease in the size of the chip, the pollution problem on the active surface of the chip is even more serious. Therefore, a packaging method is needed to prevent the active surface of the chip from being polluted.
It is an object of the present invention to provide a chip with beveled edges, which is suitable for adhering onto a die pad by an adhesive material. The chip with beveled edges comprises an active surface and a back surface, wherein the edges of the active surface are beveled. The back surface of the chip is adhered onto the surface of the die pad with adhesive material. The adhesive material preferably covers the whole surface of the chip is in a range of 30°C to 60°C, but is preferably 45°C.
It is another object of the present invention to provide a package of a semiconductor device, which comprises a carrier, a chip, an adhesive material, wires and a molding compound. The carrier has a die pad and a plurality of leads. The chip has an active surface and a corresponding back surface, and the active surface has beveled surfaces on both of its edges. The back surface of the chip is covered with adhesive material, and both sides of the chip are covered with adhesive material. The wires electrically connect the leads of the carrier to the active surfaces of the chips. The molding compound covers the chips, wires and portions between the carrier and the chips in order to allow the chip to be isolated from the outside environment.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
The present invention provides a method of fabricating a chip with beveled edges. It is an object of the present invention to provide a design of a chip that can prevent pollution of an active surface of the chip, which can be caused by an adhesive material adhering onto the active surface when excess adhesive material is applied on the chip.
Referring to
Next, the cutting machine is adjusted to the V-shaped opening to perform a singulation so that each chip can be separated to form a plurality of individual chips with beveled edges. The singulation process includes using a cutting blade to carry out the cutting process.
Referring to
The back surface 209 of the chip 204 is adhered onto a surface of a carrier such as a die pad 206 by an adhesive material 202, which covers the back surface 209 of the chip 204 to the edges of the chip 204. Thus a region 202a, which is shown in
The design of the beveled edges 210 of the chip 204 prevent the adhesive material 202 from adhering onto the active surface 208 when the adhesive material is applied to the back surface 209 of the chip 204. If the chip does not have beveled edges, the adhesive material 202 will flow to the active surface of the chip due to surface tension. Therefore, when the chip has beveled edges, the adhesive material will not be able to move up to the surface of the beveled edge 210 because the force of the surface tension is not enough to overcome the resistance force created by the surface of the beveled edge. Thus the design of the beveled edges of the chip achieves the object of keeping the active surface of the chip clean.
A wire bonding process is carried out to electrically connect a plurality of nodes of a carrier by utilizing a plurality of wires 222. The carrier can be a lead frame, which is used as an example in the preferred embodiment of the present invention. However, the scope of the present invention is not limited to types of carriers used such as the lead frame. A plurality of bonding pads (not shown) of the chip 204 are electrically connected to leads 220 by the wires 222. The wires are made of materials comprising gold and aluminum. An encapsualting process is performed to cover the chip 204, the wires 222 and a portion of the leads 220 by a molding compound 224. The molding compound 224 comprises epoxy.
A carrier 300, such as a substrate, is firstly provided. The carrier 300 comprises a die pad 306 that can locate chips 304, 404. The first chip 304 has beveled edges 310. A back surface 309 of the first chip 304 is adhered onto a surface 306a of the die pad 306 by an adhesive material 302. To ensure that the first chip 304 is adhered properly onto the die pad 306, the adhesive material is filled into a region 306a, which extends outside of the back surface 309 of the chip 304. The first chip has beveled edges to prevent the excess adhesive material from flowing to an active surface 308 of the first chip 304.
From the above-mentioned method, a second chip 404 also has beveled edges, wherein an angle of the beveled edges can be different from or the same as that of the first chip 304. The second chip 404 has an active surface 408 and a back surface 409, which is adhered onto the active surface 308 of the first chip 304 by the adhesive material 302. To ensure the second chip 404 is adhered properly onto the first chip 304, the adhesive material is filled on the active surface 308 of the first chip 304, which is larger than the second chip 404. The second chip 404 also has beveled edges to prevent the excess adhesive material from flowing to its active surface 408. Thus the active surface 408 of the second chip 404 remains clean.
Wire bonding is performed to electrically connect the first chip 304 to the second chip 404 and the first chip 304 to the carrier 300. The wires 320 electrically connect the first chip 304 and the second chip 404 to a plurality of leads of the carrier 300, wherein the leads of the carrier 300 can be gold fingers 322 of the substrate, for example. The wires 320 are made of materials comprising gold and aluminum. An encapsulating process is carried out to cover the first chip 304, the second chip 404, the wires 222 and a portion of the surface of the carrier 300 with a molding compound 324. The molding compound 224 comprises epoxy.
Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
Hsiao, Wei-Min, Chen, Jian-Cheng
Patent | Priority | Assignee | Title |
6818998, | Jun 29 2001 | Samsung Electronics Co., Ltd. | Stacked chip package having upper chip provided with trenches and method of manufacturing the same |
7084513, | Dec 07 2001 | SOCIONEXT INC | Semiconductor device having a plurality of semiconductor chips and method for manufacturing the same |
7115483, | Jun 29 2001 | Samsung Electronics Co., Ltd. | Stacked chip package having upper chip provided with trenches and method of manufacturing the same |
7253511, | Jul 13 2004 | STATS CHIPPAC PTE LTE ; STATS CHIPPAC PTE LTD | Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package |
7279361, | Sep 17 2002 | STATS CHIPPAC PTE LTE | Method for making a semiconductor multi-package module having wire bond interconnect between stacked packages |
7291926, | Dec 31 2003 | Advanced Semiconductor Engineering, Inc. | Multi-chip package structure |
7351610, | Oct 08 2002 | STATS CHIPPAC PTE LTE | Method of fabricating a semiconductor multi-package module having a second package substrate with an exposed metal layer wire bonded to a first package substrate |
7358115, | Oct 08 2002 | ChipPAC, Inc. | Method of fabricating a semiconductor assembly including chip scale package and second substrate with exposed substrate surfaces on upper and lower sides |
7364946, | Oct 08 2002 | STATS CHIPPAC PTE LTE ; STATS CHIPPAC PTE LTD | Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package |
7372141, | Mar 31 2005 | STATS CHIPPAC PTE LTE | Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides |
7394148, | Jun 20 2005 | STATS CHIPPAC PTE LTE | Module having stacked chip scale semiconductor packages |
7429786, | Apr 29 2005 | STATS CHIPPAC PTE LTE | Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides |
7429787, | Mar 31 2005 | STATS CHIPPAC PTE LTE | Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides |
7582960, | May 05 2005 | STATS CHIPPAC PTE LTE | Multiple chip package module including die stacked over encapsulated package |
7645634, | Jun 20 2005 | STATS CHIPPAC PTE LTE | Method of fabricating module having stacked chip scale semiconductor packages |
7652376, | Jan 04 2006 | STATS CHIPPAC PTE LTE | Integrated circuit package system including stacked die |
7682873, | Sep 17 2002 | STATS CHIPPAC PTE LTE | Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages |
7687313, | Oct 08 2002 | STATS CHIPPAC PTE LTE | Method of fabricating a semiconductor multi package module having an inverted package stacked over ball grid array (BGA) package |
7687315, | Apr 29 2005 | STATS CHIPPAC PTE LTE | Stacked integrated circuit package system and method of manufacture therefor |
7692279, | Jul 13 2004 | STATS CHIPPAC PTE LTE ; STATS CHIPPAC PTE LTD | Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package |
7749807, | Apr 04 2003 | STATS CHIPPAC PTE LTE | Method of fabricating a semiconductor multipackage module including a processor and memory package assemblies |
7750482, | Feb 09 2006 | STATS CHIPPAC PTE LTE | Integrated circuit package system including zero fillet resin |
7759246, | Dec 07 2001 | SOCIONEXT INC | Semiconductor device having a plurality of semiconductor chips and method for manufacturing the same |
7768125, | Jan 04 2006 | STATS CHIPPAC PTE LTE ; STATS CHIPPAC PTE LTD | Multi-chip package system |
7829382, | Jul 13 2004 | STATS ChipPAC Ltd | Method for making semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package |
7855100, | Mar 31 2005 | STATS CHIPPAC PTE LTE ; STATS CHIPPAC PTE LTD | Integrated circuit package system with an encapsulant cavity and method of fabrication thereof |
7935572, | Sep 17 2002 | STATS CHIPPAC PTE LTE | Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages |
8021924, | Mar 31 2005 | STATS CHIPPAC PTE LTE ; STATS CHIPPAC PTE LTD | Encapsulant cavity integrated circuit package system and method of fabrication thereof |
8030134, | May 24 2004 | STATS CHIPPAC PTE LTE | Stacked semiconductor package having adhesive/spacer structure and insulation |
8143100, | Sep 17 2002 | STATS CHIPPAC PTE LTE | Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages |
8309397, | Mar 31 2005 | STATS CHIPPAC PTE LTE ; STATS CHIPPAC PTE LTD | Integrated circuit packaging system with a component in an encapsulant cavity and method of fabrication thereof |
8552551, | May 24 2004 | STATS CHIPPAC PTE LTE | Adhesive/spacer island structure for stacking over wire bonded die |
8623704, | May 24 2004 | STATS CHIPPAC PTE LTE | Adhesive/spacer island structure for multiple die package |
8704349, | Feb 14 2006 | STATS CHIPPAC PTE LTE ; STATS CHIPPAC PTE LTD | Integrated circuit package system with exposed interconnects |
8970049, | Dec 17 2003 | STATS CHIPPAC PTE LTE | Multiple chip package module having inverted package stacked over die |
Patent | Priority | Assignee | Title |
6049124, | Dec 10 1997 | Intel Corporation | Semiconductor package |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Mar 29 2001 | HSIAO, WEI-MIN | Advanced Semiconductor Engineering, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 011723 | 0994 | |
Mar 30 2001 | CHEN, JIAN-CHENG | Advanced Semiconductor Engineering, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 011723 | 0994 | |
Apr 19 2001 | Advanced Semiconductor Engineering, Inc. | (assignment on the face of the patent) |
Date | Maintenance Fee Events |
Sep 04 2007 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Sep 10 2007 | REM: Maintenance Fee Reminder Mailed. |
Sep 02 2011 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Sep 02 2015 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Mar 02 2007 | 4 years fee payment window open |
Sep 02 2007 | 6 months grace period start (w surcharge) |
Mar 02 2008 | patent expiry (for year 4) |
Mar 02 2010 | 2 years to revive unintentionally abandoned end. (for year 4) |
Mar 02 2011 | 8 years fee payment window open |
Sep 02 2011 | 6 months grace period start (w surcharge) |
Mar 02 2012 | patent expiry (for year 8) |
Mar 02 2014 | 2 years to revive unintentionally abandoned end. (for year 8) |
Mar 02 2015 | 12 years fee payment window open |
Sep 02 2015 | 6 months grace period start (w surcharge) |
Mar 02 2016 | patent expiry (for year 12) |
Mar 02 2018 | 2 years to revive unintentionally abandoned end. (for year 12) |