A semiconductor device includes a semiconductor material, the semiconductor material including a base region and a field stop zone including a first side adjacent the base region and a second side opposite the first side. The field stop zone includes a first dopant implant and a second dopant implant. The first dopant implant has a first dopant concentration maximum and the second dopant implant has a second dopant concentration maximum with the first dopant concentration maximum being less than the second dopant concentration maximum, and being located closer to the second side than the second dopant concentration maximum.
|
14. A semiconductor device comprising:
a semiconductor material, the semiconductor material including a base region and a field stop zone including a first side adjacent the base region and a second side opposite the first side, the field stop zone having a dopant concentration profile beginning at the second side, the dopant concentration profile having a plurality of maxima including a first concentration maximum, a second concentration maximum and a third concentration maximum located respectively away from the second side, the second dopant concentration maximum being at least ten percent lower than the first and third dopant concentration maxima.
1. A semiconductor device comprising:
a semiconductor material, the semiconductor material including a base region and a field stop zone including a first side adjacent the base region and a second side opposite the first side,
the field stop zone including a first dopant implant and a second dopant implant, the first dopant implant having a first dopant concentration maximum and the second dopant implant having a second dopant concentration maximum,
the first dopant concentration maximum being less than the second dopant concentration maximum, and being located closer to the second side than the second dopant concentration maximum; and
the semiconductor material having a pn junction spaced apart from the field stop zone, the pn junction being located closer to the first side than the second side.
13. A semiconductor device comprising:
a semiconductor material, the semiconductor material including a base region and a field stop zone including a first side adjacent the base region and a second side opposite the first side, the field stop zone having a dopant concentration profile beginning at the second side, the dopant concentration profile having a plurality of maxima including a first concentration maximum and a second concentration maximum,
the first dopant concentration maximum being located closer to the second side than the second dopant concentration maximum and having a concentration less than half of the second dopant concentration maximum; and
the semiconductor material having a pn junction spaced apart from the field stop zone, the pn junction being located closer to the first side than the second side.
12. A semiconductor device comprising:
a semiconductor material, the semiconductor material including a base region and a field stop zone including a first side adjacent the base region and a second side opposite the first side, the field stop zone having a dopant concentration profile beginning at the second side,
the dopant concentration profile having a plurality of maxima including a first concentration maximum and a second concentration maximum, the first dopant concentration maximum being closer to the second field stop zone side and smaller than the second dopant concentration maximum and having a concentration value of at least 1E14 per cubic centimeter; and
the semiconductor material having a pn junction spaced apart from the field stop zone, the pn junction being located closer to the first side than the second side.
2. The semiconductor device as recited in
3. The semiconductor device as recited in
4. The semiconductor device as recited in
5. The semiconductor device as recited in
6. The semiconductor device as recited in
7. The semiconductor device as recited in
8. The semiconductor device as recited in
9. The semiconductor device as recited in
10. The semiconductor device as recited in
11. The semiconductor device as recited in
|
The present invention relates to semiconductor components such as IGBTs (insulated gate bipolar transistors), diodes and thyristors having a field stop zone.
A field stop zone typically is located adjacent an n-base layer. The field stop zone thus may define two sides, with a side adjacent the n-base layer, and a side away from the n-base layer. In an IGBT, a p-type collector layer typically borders the side away from the base layer. In a modified design, the field stop zone can also be surrounded by the n-base layer. In this case, the side adjacent the n-base layer is defined as the side of the n-base layer which is farther away from the p-type collector. While the field stop zone typically is a doped area of an n material, in some semiconductor components it may be a doped area of a p material.
It is known to provide more than one dopant implant in the field stop zone, with the highest concentration implant nearest the side away from the base material.
The present invention will be further elucidated with reference to the embodiments of the drawings, in which:
A base material 20 made of a semiconductor material such as silicon has a p base region 22 introduced on an n-base region 24. A pn junction thus is formed for the device 10. An n+ emitter region 36 is located on the p base region 22.
The field stop zone has a side 30 facing away from the base region 24, and a side 32 adjacent the base region 24 and which can be defined as the area where an implanted dopant concentration approaches or reaches the dopant concentration level of the n− base region 24.
A dopant concentration profile 34 thus can be defined with increasing depth from side 30 to side 32.
A p emitter layer 28 is adjacent the field stop side 30 and is in contact with anode contact 14.
When a voltage applied to the gate electrode 16 exceeds a threshold voltage of the device, the IGBT is turned on and the resistance in the base region 24 is reduced between the cathode contact 12 and anode contact 14.
When the voltage at the gate electrode 16 is less than the threshold voltage, current flow between contacts 12, 14 will be blocked by the pn junction.
As shown in
The semiconductor material which forms n-base region 24 is also used as the basis for a field stop zone 26, and the dopant implants 42, 44, 46, 48 are formed by creating defects in the silicon structure of the semiconductor material. For example, the dopant implants may be formed via proton implantations. After the proton implantations, the semiconductor material is subjected to heat treatment during an annealing step. Vacancy/hydrogen-related complexes are created which form donors in the field stop zone 26, and the number of donors per volume defines the dopant concentration.
A first dopant implant 42 has a dopant concentration maximum 52 and a second dopant implant 44 having a dopant concentration maximum 54. First dopant implant 52 may be formed for example by a proton implantation at at least 500 keV, for example at 550 keV. For this energy, the dopant concentration maximum 52 is located at a depth of about 6.5 micrometers. It may preferably have a dopant concentration of (1-5)E14/cubic centimeter for example. The second dopant implant 44 may be produced using a proton implantation at a higher energy than used during the first implantation, for example at an energy of 800 keV, and in this first embodiment advantageously provides a second dopant concentration maximum 54 with a concentration greater than the dopant concentration maximum 52, for example at (1-5)E15/cubic centimeter or ten times the amount of the first dopant concentration maximum 52. The second dopant concentration maximum 54 preferably is at least twice the amount of the first dopant concentration maximum 52. The second dopant concentration maximum 54 also is located further away from side 30, for example at about 11 micrometers.
The doping profile 34 of the present invention with the two maxima 52, 54 can optimize the turn-off response of the IGBT so that good leakage current characteristics and good short circuit ruggedness may be provided.
It is also desirable that turn-off response be soft. For such an effect, two further implants 46, 48 for example may be provided. Implant 46 may occur for example via a proton implantation at 1200 keV and provide a dopant concentration maximum 56 located at about 20 micrometer depth and with a dopant concentration of for example 5E13-2E14/cubic centimeter. Implant 48 may occur for example using a proton implantation at 1500 keV with a dopant concentration maximum 58 of for example (1-5)E13/cubic centimeter located at a depth of about 30 micrometers.
The solid line in
It is noted that the concentration scale is logarithmic and thus minor dopant concentrations of the second implant 44, for example, at a depth of about 6.5 micrometers, have little effect on the maximum of the profile 34 caused by first maximum 52 of first implant 52.
The implants may be produced by proton implantation from the direction of side 30, in other words the back of a wafer containing the n-base material. After the implantations, the wafer may then be annealed at for example temperatures of 300° C.-500° C. for 30 min. to 4 hrs in order to activate the hydrogen-related donors and to reduce the concentration of recombination centers such as, for example, di-vacancies or oxygen-vacancy complexes. This annealing step can result in a broadening of the donor peaks.
Alternate methods to create the profile of the present invention such as implantations through the front of the wafer however may also be possible.
As opposed to proton implantation, another option is a multiple helium implantation in combination with a controlled formation of thermal donors. Furthermore, other dopants such as phosphorus or arsenic are also possible.
The depths of the maxima may be set via an appropriate selection of the acceleration energies for the individual implants and are freely selectable in principle.
Prior art field stop zone dopant profiles often had good short circuit ruggedness but poor leakage current yields for switching, typically where the maximum was located too close to the side away from the base material. The increase in leakage current can be explained by doping inhomogeneities in the implanted region. These doping inhomogeneities are induced by particles adhering on the wafer surface during implantation and, thus, locally reducing the penetration depth of the implanted ions. Other known dopant profiles may have had good leakage current yields, but had poor short circuit ruggedness, typically where the doping maximum was located further away from the side away from the base material.
The present profile advantageously provides for excellent short-circuit ruggedness of the IGBT. Holes are delivered from the p emitter 28, and the holes partly compensate for a negative space charge on the anode side, so that the electric field gradient, and thus the maximum electric field intensity, does not assume excessively high values near the anode contact 14 when the electric field is switched over during short-circuit operation. Increased hole injection may be achieved since dopant maximum 52 has a lower dopant concentration than dopant maximum 54. This relationship also reduces the current-dependence of the emitter efficiency of the anode-side pn junction in the IGBT. For a soft decay of the current in the end phase of the switching response during turn off, the present profile also advantageously raises the charge carrier concentration between the side 30 and the second maximum 54. A sufficient amount of charge carriers in this area is available even during the end phase of the reverse recovery phase, so that the dI/dt (change in current with respect to change in time) gradient of current decay is sufficiently low and excessive overvoltages across parasitic inductivities are avoided.
Another advantage of the profile 34 is that the leakage current yield can be substantially improved. Using higher implantation energies, the radiation passes through even larger particles located on the semiconductor surface during the implantation process. A higher dopant concentration in the second implant compared to the first implant therefore delivers a better leakage current yield than in the reverse case.
P emitter 28 may be a shallow profile emitter. However, emitter variants may include, for example, thermally diffused p-emitters or p-emitters manufactured by laser annealing or emitters manufactured by a combination of these methods. In particular, annealed emitters have the advantage of a greater lateral homogeneity. Emitters manufactured in this way are characterized by higher emitting efficiency which may be further adjusted via a field stop profile according to the present invention, so that leakage currents and switching loss at nominal current and lower currents are reduced. In contrast, in the event of a short circuit, the profile has almost no effect on the emitter efficiency due to the high charge carrier concentration, as is desired.
While the field stop zone profile has been described with n channel devices, it may also be used with p channel type devices.
Strack, Helmut, Pfirsch, Frank, Schulze, Hans-Joachim, Niedernostheide, Franz-Josef, Schaeffer, Carsten
Patent | Priority | Assignee | Title |
10014387, | Jun 27 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Semiconductor structure with multiple transistors having various threshold voltages |
10026803, | Dec 27 2016 | Mitsubishi Electric Corporation | Semiconductor device, power conversion device, and method of manufacturing semiconductor device |
10074568, | Sep 30 2009 | MIE FUJITSU SEMICONDUCTOR LIMITED | Electronic devices and systems, and methods for making and using same |
10134886, | Mar 16 2016 | Semiconductor Components Industries, LLC | Insulated gate bipolar device and manufacturing method thereof |
10170559, | Jun 29 2017 | ALPHA AND OMEGA SEMICONDUCTOR CAYMAN LTD | Reverse conducting IGBT incorporating epitaxial layer field stop zone and fabrication method |
10217668, | Sep 30 2009 | MIE FUJITSU SEMICONDUCTOR LIMITED | Electronic devices and systems, and methods for making and using the same |
10217838, | Jun 27 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Semiconductor structure with multiple transistors having various threshold voltages |
10224244, | Sep 30 2009 | MIE FUJITSU SEMICONDUCTOR LIMITED | Electronic devices and systems, and methods for making and using the same |
10229972, | Jun 17 2015 | Fuji Electric Co., Ltd. | Semiconductor device |
10250257, | Feb 18 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Digital circuits having improved transistors, and methods therefor |
10325986, | Sep 30 2009 | MIE FUJITSU SEMICONDUCTOR LIMITED | Advanced transistors with punch through suppression |
10415154, | Dec 02 2015 | Mitsubishi Electric Corporation | Silicon carbide epitaxial substrate and silicon carbide semiconductor device |
10573644, | Dec 09 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Tipless transistors, short-tip transistors, and methods and circuits therefor |
10686038, | Jun 29 2017 | ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. | Reverse conducting IGBT incorporating epitaxial layer field stop zone |
10738393, | Dec 02 2015 | Mitsubishi Electric Corporation | Silicon carbide epitaxial substrate and silicon carbide semiconductor device |
10774441, | Dec 02 2015 | Mitsubishi Electric Corporation | Silicon carbide epitaxial substrate and silicon carbide semiconductor device |
10833021, | Jun 29 2017 | ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.; ALPHA AND OMEGA SEMICONDUCTOR CAYMAN LTD | Method for precisely aligning backside pattern to frontside pattern of a semiconductor wafer |
10995420, | Dec 02 2015 | Mitsubishi Electric Corporation | Silicon carbide epitaxial substrate and silicon carbide semiconductor device |
11031465, | Jun 29 2017 | ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. | Semiconductor device incorporating epitaxial layer field stop zone |
11062950, | Sep 30 2009 | UNITED SEMICONDUCTOR JAPAN CO , LTD | Electronic devices and systems, and methods for making and using the same |
11101133, | Aug 17 2018 | Mitsubishi Electric Corporation | Semiconductor device and manufacturing method thereof |
11145647, | Dec 09 2011 | United Semiconductor Japan Co., Ltd. | Tipless transistors, short-tip transistors, and methods and circuits therefor |
11749716, | Jun 29 2017 | ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. | Semiconductor device incorporating epitaxial layer field stop zone |
11887895, | Sep 30 2009 | United Semiconductor Japan Co., Ltd. | Electronic devices and systems, and methods for making and using the same |
11949007, | Nov 02 2020 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing semiconductor device |
8273617, | Sep 30 2009 | MIE FUJITSU SEMICONDUCTOR LIMITED | Electronic devices and systems, and methods for making and using the same |
8377783, | Sep 30 2010 | MIE FUJITSU SEMICONDUCTOR LIMITED | Method for reducing punch-through in a transistor device |
8400219, | Mar 24 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Analog circuits having improved transistors, and methods therefor |
8404551, | Dec 03 2010 | MIE FUJITSU SEMICONDUCTOR LIMITED | Source/drain extension control for advanced transistors |
8421162, | Sep 30 2009 | MIE FUJITSU SEMICONDUCTOR LIMITED | Advanced transistors with punch through suppression |
8461875, | Feb 18 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Digital circuits having improved transistors, and methods therefor |
8525271, | Mar 03 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Semiconductor structure with improved channel stack and method for fabrication thereof |
8530286, | Apr 12 2010 | MIE FUJITSU SEMICONDUCTOR LIMITED | Low power semiconductor transistor structure and method of fabrication thereof |
8541824, | Sep 30 2009 | MIE FUJITSU SEMICONDUCTOR LIMITED | Electronic devices and systems, and methods for making and using the same |
8563384, | Dec 03 2010 | MIE FUJITSU SEMICONDUCTOR LIMITED | Source/drain extension control for advanced transistors |
8569128, | Jun 21 2010 | MIE FUJITSU SEMICONDUCTOR LIMITED | Semiconductor structure and method of fabrication thereof with mixed metal types |
8569156, | May 16 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Reducing or eliminating pre-amorphization in transistor manufacture |
8599623, | Dec 23 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Circuits and methods for measuring circuit elements in an integrated circuit device |
8604527, | Sep 30 2009 | MIE FUJITSU SEMICONDUCTOR LIMITED | Electronic devices and systems, and methods for making and using the same |
8604530, | Sep 30 2009 | MIE FUJITSU SEMICONDUCTOR LIMITED | Electronic devices and systems, and methods for making and using the same |
8614128, | Aug 23 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | CMOS structures and processes based on selective thinning |
8629016, | Jul 26 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer |
8637955, | Aug 31 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Semiconductor structure with reduced junction leakage and method of fabrication thereof |
8645878, | Aug 23 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Porting a circuit design from a first semiconductor process to a second semiconductor process |
8653604, | Jul 26 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer |
8686511, | Dec 03 2010 | MIE FUJITSU SEMICONDUCTOR LIMITED | Source/drain extension control for advanced transistors |
8713511, | Sep 16 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Tools and methods for yield-aware semiconductor manufacturing process target generation |
8735987, | Jun 06 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | CMOS gate stack structures and processes |
8748270, | Mar 30 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Process for manufacturing an improved analog transistor |
8748986, | Aug 05 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Electronic device with controlled threshold voltage |
8759872, | Jun 22 2010 | MIE FUJITSU SEMICONDUCTOR LIMITED | Transistor with threshold voltage set notch and method of fabrication thereof |
8796048, | May 11 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Monitoring and measurement of thin film layers |
8806395, | Aug 23 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Porting a circuit design from a first semiconductor process to a second semiconductor process |
8811068, | May 13 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Integrated circuit devices and methods |
8816754, | Nov 02 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Body bias circuits and methods |
8819603, | Dec 15 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Memory circuits and methods of making and designing the same |
8847684, | Mar 24 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Analog circuits having improved transistors, and methods therefor |
8863064, | Mar 23 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | SRAM cell layout structure and devices therefrom |
8877619, | Jan 23 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom |
8883600, | Dec 22 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Transistor having reduced junction leakage and methods of forming thereof |
8895327, | Dec 09 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Tipless transistors, short-tip transistors, and methods and circuits therefor |
8916937, | Jul 26 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer |
8937005, | May 16 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Reducing or eliminating pre-amorphization in transistor manufacture |
8963249, | Aug 05 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Electronic device with controlled threshold voltage |
8970289, | Jan 23 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Circuits and devices for generating bi-directional body bias voltages, and methods therefor |
8975128, | Sep 30 2009 | MIE FUJITSU SEMICONDUCTOR LIMITED | Electronic devices and systems, and methods for making and using the same |
8976575, | Aug 29 2013 | MIE FUJITSU SEMICONDUCTOR LIMITED | SRAM performance monitor |
8988153, | Mar 09 2013 | MIE FUJITSU SEMICONDUCTOR LIMITED | Ring oscillator with NMOS or PMOS variation insensitivity |
8994415, | Mar 01 2013 | MIE FUJITSU SEMICONDUCTOR LIMITED | Multiple VDD clock buffer |
8995204, | Jun 23 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Circuit devices and methods having adjustable transistor body bias |
8999861, | May 11 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Semiconductor structure with substitutional boron and method for fabrication thereof |
9006843, | Dec 03 2010 | MIE FUJITSU SEMICONDUCTOR LIMITED | Source/drain extension control for advanced transistors |
9041126, | Sep 21 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Deeply depleted MOS transistors having a screening layer and methods thereof |
9054219, | Aug 05 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Semiconductor devices having fin structures and fabrication methods thereof |
9070477, | Dec 12 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Bit interleaved low voltage static random access memory (SRAM) and related methods |
9093469, | Mar 30 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Analog transistor |
9093550, | Jan 31 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same |
9093997, | Nov 15 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Slew based process and bias monitors and related methods |
9105711, | Aug 31 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Semiconductor structure with reduced junction leakage and method of fabrication thereof |
9111785, | Mar 03 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Semiconductor structure with improved channel stack and method for fabrication thereof |
9112057, | Sep 18 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Semiconductor devices with dopant migration suppression and method of fabrication thereof |
9112484, | Dec 20 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Integrated circuit process and bias monitors and related methods |
9112495, | Mar 15 2013 | MIE FUJITSU SEMICONDUCTOR LIMITED | Integrated circuit device body bias circuits and methods |
9117746, | Aug 23 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Porting a circuit design from a first semiconductor process to a second semiconductor process |
9129851, | Nov 30 2011 | Denso Corporation | Semiconductor device |
9154123, | Nov 02 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Body bias circuits and methods |
9184750, | Feb 18 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Digital circuits having improved transistors, and methods therefor |
9196727, | Dec 22 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | High uniformity screen and epitaxial layers for CMOS devices |
9224733, | Jun 21 2010 | MIE FUJITSU SEMICONDUCTOR LIMITED | Semiconductor structure and method of fabrication thereof with mixed metal types |
9231541, | Mar 24 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Analog circuits having improved transistors, and methods therefor |
9236466, | Oct 07 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Analog circuits having improved insulated gate transistors, and methods therefor |
9263523, | Sep 30 2009 | MIE FUJITSU SEMICONDUCTOR LIMITED | Advanced transistors with punch through suppression |
9268885, | Feb 28 2013 | MIE FUJITSU SEMICONDUCTOR LIMITED | Integrated circuit device methods and models with predicted device metric variations |
9276561, | Dec 20 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Integrated circuit process and bias monitors and related methods |
9281248, | Jun 06 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | CMOS gate stack structures and processes |
9297850, | Dec 23 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Circuits and methods for measuring circuit elements in an integrated circuit device |
9299698, | Jun 27 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Semiconductor structure with multiple transistors having various threshold voltages |
9299801, | Mar 14 2013 | MIE FUJITSU SEMICONDUCTOR LIMITED | Method for fabricating a transistor device with a tuned dopant profile |
9319013, | Aug 19 2014 | MIE FUJITSU SEMICONDUCTOR LIMITED | Operational amplifier input offset correction with transistor threshold voltage adjustment |
9319034, | Nov 15 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Slew based process and bias monitors and related methods |
9362291, | May 13 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Integrated circuit devices and methods |
9368624, | Dec 22 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Method for fabricating a transistor with reduced junction leakage current |
9385047, | Jan 31 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same |
9385121, | Dec 09 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Tipless transistors, short-tip transistors, and methods and circuits therefor |
9391076, | Aug 23 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | CMOS structures and processes based on selective thinning |
9406567, | Feb 28 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Method for fabricating multiple transistor devices on a substrate with varying threshold voltages |
9418987, | Jun 22 2010 | MIE FUJITSU SEMICONDUCTOR LIMITED | Transistor with threshold voltage set notch and method of fabrication thereof |
9424385, | Mar 23 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | SRAM cell layout structure and devices therefrom |
9431068, | Oct 31 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Dynamic random access memory (DRAM) with low variation transistor peripheral circuits |
9449967, | Mar 15 2013 | MIE FUJITSU SEMICONDUCTOR LIMITED | Transistor array structure |
9478571, | May 24 2013 | MIE FUJITSU SEMICONDUCTOR LIMITED | Buried channel deeply depleted channel transistor |
9496261, | Apr 12 2010 | MIE FUJITSU SEMICONDUCTOR LIMITED | Low power semiconductor transistor structure and method of fabrication thereof |
9508728, | Jun 06 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | CMOS gate stack structures and processes |
9508800, | Sep 30 2009 | MIE FUJITSU SEMICONDUCTOR LIMITED | Advanced transistors with punch through suppression |
9514940, | May 16 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Reducing or eliminating pre-amorphization in transistor manufacture |
9548086, | Mar 15 2013 | MIE FUJITSU SEMICONDUCTOR LIMITED | Integrated circuit device body bias circuits and methods |
9577041, | Mar 14 2013 | MIE FUJITSU SEMICONDUCTOR LIMITED | Method for fabricating a transistor device with a tuned dopant profile |
9583484, | Dec 09 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Tipless transistors, short-tip transistors, and methods and circuits therefor |
9680470, | Feb 18 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Digital circuits having improved transistors, and methods therefor |
9710006, | Jul 25 2014 | MIE FUJITSU SEMICONDUCTOR LIMITED | Power up body bias circuits and methods |
9741428, | May 13 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Integrated circuit devices and methods |
9768285, | Mar 16 2016 | Semiconductor Components Industries, LLC | Semiconductor device and method of manufacture |
9773873, | Mar 18 2016 | Mitsubishi Electric Corporation | Semiconductor device |
9786703, | May 24 2013 | MIE FUJITSU SEMICONDUCTOR LIMITED | Buried channel deeply depleted channel transistor |
9793172, | May 16 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Reducing or eliminating pre-amorphization in transistor manufacture |
9812550, | Jun 27 2012 | MIE FUJITSU SEMICONDUCTOR LIMITED | Semiconductor structure with multiple transistors having various threshold voltages |
9838012, | Feb 18 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Digital circuits having improved transistors, and methods therefor |
9853019, | Mar 15 2013 | MIE FUJITSU SEMICONDUCTOR LIMITED | Integrated circuit device body bias circuits and methods |
9865596, | Apr 12 2010 | MIE FUJITSU SEMICONDUCTOR LIMITED | Low power semiconductor transistor structure and method of fabrication thereof |
9893148, | Mar 14 2013 | MIE FUJITSU SEMICONDUCTOR LIMITED | Method for fabricating a transistor device with a tuned dopant profile |
9922977, | Jun 22 2010 | MIE FUJITSU SEMICONDUCTOR LIMITED | Transistor with threshold voltage set notch and method of fabrication thereof |
9953974, | Dec 09 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Tipless transistors, short-tip transistors, and methods and circuits therefor |
9966130, | May 13 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Integrated circuit devices and methods |
9985631, | Feb 18 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Digital circuits having improved transistors, and methods therefor |
9991300, | May 24 2013 | MIE FUJITSU SEMICONDUCTOR LIMITED | Buried channel deeply depleted channel transistor |
Patent | Priority | Assignee | Title |
5006477, | Nov 25 1988 | Hughes Aircraft Company | Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices |
6482681, | May 05 2000 | Infineon Technologies Americas Corp | Hydrogen implant for buffer zone of punch-through non epi IGBT |
6559023, | Feb 09 2001 | FUJI ELECTRIC CO , LTD | Method of fabricating a semiconductor device with phosphorous and boron ion implantation, and by annealing to control impurity concentration thereof |
6696705, | Jan 12 2000 | INFINEON TECHNOLOGIES BIPOLAR GMBH & CO KG | Power semiconductor component having a mesa edge termination |
6707111, | May 05 2000 | Infineon Technologies Americas Corp | Hydrogen implant for buffer zone of punch-through non EPI IGBT |
6770917, | Sep 22 2000 | Infineon Technologies AG; EUPEC EUROPAISCHE GESELLSCHAFT FUR LEISTUNGSHALB-LEITER MBH & CO KG | High-voltage diode |
6924177, | Mar 02 1999 | Infineon Technologies AG | Method for producing a thyristor |
7005761, | May 19 2000 | Infineon Technologies AG | Circuit configuration for off-load switching, switch mode power supply, clocked supply, voltage regulator, lamp switch, and methods for operating the circuit configuration |
20020190281, | |||
20050164476, | |||
20050215042, | |||
20060081923, | |||
DE3339393, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jun 23 2006 | SCHULZE, HANS-JOACHIM | Infineon Technologies Austria AG | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 018080 | /0966 | |
Jun 23 2006 | NIEDERNOSTHEIDE, FRANZ JOSEF | Infineon Technologies Austria AG | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 018080 | /0966 | |
Jun 23 2006 | PFIRSCH, FRANK | Infineon Technologies Austria AG | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 018080 | /0966 | |
Jun 26 2006 | STRACK, HELMUT | Infineon Technologies Austria AG | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 018080 | /0966 | |
Jun 29 2006 | SCHAEFFER, CARSTEN | Infineon Technologies Austria AG | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 018080 | /0966 | |
Jun 30 2006 | Infineon Technologies Austria AG | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Jul 09 2009 | ASPN: Payor Number Assigned. |
Jul 09 2009 | RMPN: Payer Number De-assigned. |
Nov 22 2012 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Nov 15 2016 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Nov 18 2020 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
May 26 2012 | 4 years fee payment window open |
Nov 26 2012 | 6 months grace period start (w surcharge) |
May 26 2013 | patent expiry (for year 4) |
May 26 2015 | 2 years to revive unintentionally abandoned end. (for year 4) |
May 26 2016 | 8 years fee payment window open |
Nov 26 2016 | 6 months grace period start (w surcharge) |
May 26 2017 | patent expiry (for year 8) |
May 26 2019 | 2 years to revive unintentionally abandoned end. (for year 8) |
May 26 2020 | 12 years fee payment window open |
Nov 26 2020 | 6 months grace period start (w surcharge) |
May 26 2021 | patent expiry (for year 12) |
May 26 2023 | 2 years to revive unintentionally abandoned end. (for year 12) |