A semiconductor device includes a semiconductor material, the semiconductor material including a base region and a field stop zone including a first side adjacent the base region and a second side opposite the first side. The field stop zone includes a first dopant implant and a second dopant implant. The first dopant implant has a first dopant concentration maximum and the second dopant implant has a second dopant concentration maximum with the first dopant concentration maximum being less than the second dopant concentration maximum, and being located closer to the second side than the second dopant concentration maximum.

Patent
   7538412
Priority
Jun 30 2006
Filed
Jun 30 2006
Issued
May 26 2009
Expiry
Jan 10 2027
Extension
194 days
Assg.orig
Entity
Large
135
13
all paid
14. A semiconductor device comprising:
a semiconductor material, the semiconductor material including a base region and a field stop zone including a first side adjacent the base region and a second side opposite the first side, the field stop zone having a dopant concentration profile beginning at the second side, the dopant concentration profile having a plurality of maxima including a first concentration maximum, a second concentration maximum and a third concentration maximum located respectively away from the second side, the second dopant concentration maximum being at least ten percent lower than the first and third dopant concentration maxima.
1. A semiconductor device comprising:
a semiconductor material, the semiconductor material including a base region and a field stop zone including a first side adjacent the base region and a second side opposite the first side,
the field stop zone including a first dopant implant and a second dopant implant, the first dopant implant having a first dopant concentration maximum and the second dopant implant having a second dopant concentration maximum,
the first dopant concentration maximum being less than the second dopant concentration maximum, and being located closer to the second side than the second dopant concentration maximum; and
the semiconductor material having a pn junction spaced apart from the field stop zone, the pn junction being located closer to the first side than the second side.
13. A semiconductor device comprising:
a semiconductor material, the semiconductor material including a base region and a field stop zone including a first side adjacent the base region and a second side opposite the first side, the field stop zone having a dopant concentration profile beginning at the second side, the dopant concentration profile having a plurality of maxima including a first concentration maximum and a second concentration maximum,
the first dopant concentration maximum being located closer to the second side than the second dopant concentration maximum and having a concentration less than half of the second dopant concentration maximum; and
the semiconductor material having a pn junction spaced apart from the field stop zone, the pn junction being located closer to the first side than the second side.
12. A semiconductor device comprising:
a semiconductor material, the semiconductor material including a base region and a field stop zone including a first side adjacent the base region and a second side opposite the first side, the field stop zone having a dopant concentration profile beginning at the second side,
the dopant concentration profile having a plurality of maxima including a first concentration maximum and a second concentration maximum, the first dopant concentration maximum being closer to the second field stop zone side and smaller than the second dopant concentration maximum and having a concentration value of at least 1E14 per cubic centimeter; and
the semiconductor material having a pn junction spaced apart from the field stop zone, the pn junction being located closer to the first side than the second side.
2. The semiconductor device as recited in claim 1 wherein the first dopant concentration maximum is at least 1E14 per cubic centimeter.
3. The semiconductor device as recited in claim 1 wherein the first dopant implant includes vacancy/hydrogen-related complexes.
4. The semiconductor device as recited in claim 1 wherein the first and second dopant implant include vacancy/hydrogen-related complexes.
5. The semiconductor device as recited in claim 1 wherein the device is an IGBT, the base region including a p base region and an n base region contacting the p base region, and the device further includes a p-emitter adjacent the second side.
6. The semiconductor device as recited in claim 1 wherein the field stop zone includes a third dopant implant, the third dopant implant having a third dopant concentration maximum located further away from the second side than the second dopant concentration maximum, the third dopant concentration maximum being less than the second dopant concentration maximum.
7. The semiconductor device as recited in claim 6 wherein the field stop zone includes a fourth dopant implant, the fourth dopant implant having a fourth dopant concentration maximum located further away from the second side than the third dopant concentration maximum, the fourth dopant concentration maximum being less than the third dopant concentration maximum.
8. The semiconductor device as recited in claim 6 wherein the field stop zone includes a fourth dopant implant, the fourth dopant implant having a fourth dopant concentration maximum located further away from the second side than the third dopant concentration maximum, the fourth dopant concentration maximum being equal or greater than the third or the second or the first dopant concentration maxima.
9. The semiconductor device as recited in claim 6 wherein the third dopant concentration maximum is less than half the second dopant concentration maximum.
10. The semiconductor device as recited in claim 9 wherein the third dopant concentration is less than a third of the second dopant concentration maximum.
11. The semiconductor device as recited in claim 1 wherein the device is a diode, the base region including an n− base region and the device further comprising a p emitter adjacent the n− base region.

The present invention relates to semiconductor components such as IGBTs (insulated gate bipolar transistors), diodes and thyristors having a field stop zone.

A field stop zone typically is located adjacent an n-base layer. The field stop zone thus may define two sides, with a side adjacent the n-base layer, and a side away from the n-base layer. In an IGBT, a p-type collector layer typically borders the side away from the base layer. In a modified design, the field stop zone can also be surrounded by the n-base layer. In this case, the side adjacent the n-base layer is defined as the side of the n-base layer which is farther away from the p-type collector. While the field stop zone typically is a doped area of an n material, in some semiconductor components it may be a doped area of a p material.

It is known to provide more than one dopant implant in the field stop zone, with the highest concentration implant nearest the side away from the base material.

The present invention will be further elucidated with reference to the embodiments of the drawings, in which:

FIG. 1 shows schematically an embodiment of the present invention with an IGBT including a field stop zone;

FIGS. 2a, 2b and 2c show schematically possible field stop zone dopant profiles according to a first embodiment of the present invention; and

FIG. 3 shows schematically a further possible field stop zone dopant profile according to another embodiment of the present invention; and

FIG. 4 shows schematically an embodiment of the present invention with a diode having a field stop zone.

FIG. 1 shows schematically an embodiment of the present invention with an IGBT 10 having an emitter or cathode electrical contact 12 and a collector or anode electrical contact 14, both made for example of copper or aluminium. A gate electrode 16, made for example of polycrystalline silicon, is located in a dielectric material layer 18, made for example of silicon dioxide.

A base material 20 made of a semiconductor material such as silicon has a p base region 22 introduced on an n-base region 24. A pn junction thus is formed for the device 10. An n+ emitter region 36 is located on the p base region 22.

The field stop zone has a side 30 facing away from the base region 24, and a side 32 adjacent the base region 24 and which can be defined as the area where an implanted dopant concentration approaches or reaches the dopant concentration level of the n− base region 24.

A dopant concentration profile 34 thus can be defined with increasing depth from side 30 to side 32.

A p emitter layer 28 is adjacent the field stop side 30 and is in contact with anode contact 14.

When a voltage applied to the gate electrode 16 exceeds a threshold voltage of the device, the IGBT is turned on and the resistance in the base region 24 is reduced between the cathode contact 12 and anode contact 14.

When the voltage at the gate electrode 16 is less than the threshold voltage, current flow between contacts 12, 14 will be blocked by the pn junction.

As shown in FIG. 2a, the present invention provides in a first embodiment that the field stop zone profile 34 is formed by a plurality of dopant implants 42, 44, 46, 48.

The semiconductor material which forms n-base region 24 is also used as the basis for a field stop zone 26, and the dopant implants 42, 44, 46, 48 are formed by creating defects in the silicon structure of the semiconductor material. For example, the dopant implants may be formed via proton implantations. After the proton implantations, the semiconductor material is subjected to heat treatment during an annealing step. Vacancy/hydrogen-related complexes are created which form donors in the field stop zone 26, and the number of donors per volume defines the dopant concentration.

A first dopant implant 42 has a dopant concentration maximum 52 and a second dopant implant 44 having a dopant concentration maximum 54. First dopant implant 52 may be formed for example by a proton implantation at at least 500 keV, for example at 550 keV. For this energy, the dopant concentration maximum 52 is located at a depth of about 6.5 micrometers. It may preferably have a dopant concentration of (1-5)E14/cubic centimeter for example. The second dopant implant 44 may be produced using a proton implantation at a higher energy than used during the first implantation, for example at an energy of 800 keV, and in this first embodiment advantageously provides a second dopant concentration maximum 54 with a concentration greater than the dopant concentration maximum 52, for example at (1-5)E15/cubic centimeter or ten times the amount of the first dopant concentration maximum 52. The second dopant concentration maximum 54 preferably is at least twice the amount of the first dopant concentration maximum 52. The second dopant concentration maximum 54 also is located further away from side 30, for example at about 11 micrometers.

The doping profile 34 of the present invention with the two maxima 52, 54 can optimize the turn-off response of the IGBT so that good leakage current characteristics and good short circuit ruggedness may be provided.

It is also desirable that turn-off response be soft. For such an effect, two further implants 46, 48 for example may be provided. Implant 46 may occur for example via a proton implantation at 1200 keV and provide a dopant concentration maximum 56 located at about 20 micrometer depth and with a dopant concentration of for example 5E13-2E14/cubic centimeter. Implant 48 may occur for example using a proton implantation at 1500 keV with a dopant concentration maximum 58 of for example (1-5)E13/cubic centimeter located at a depth of about 30 micrometers.

The solid line in FIG. 2a thus represents the actual dopant profile through field stop zone 26, with the dashed lines showing the dopant concentration of each implant 42, 44, 46, 48. The dotted line shows the envelope of the actual dopant profile.

It is noted that the concentration scale is logarithmic and thus minor dopant concentrations of the second implant 44, for example, at a depth of about 6.5 micrometers, have little effect on the maximum of the profile 34 caused by first maximum 52 of first implant 52.

FIGS. 2b and 2c show other further possible profiles 34a and 34b, respectively, according to the first embodiment. The field stop zone of FIG. 2b has a fourth implant 48a having a fourth peak 58a having a maximum dopant concentration approximately equal to the maximum dopant concentration of peak 54. The field stop zone 58b of FIG. 2c has a fourth implant 48b having a maximum dopant concentration greater than the maximum dopant concentration of all other peaks 52, 54, 56

The implants may be produced by proton implantation from the direction of side 30, in other words the back of a wafer containing the n-base material. After the implantations, the wafer may then be annealed at for example temperatures of 300° C.-500° C. for 30 min. to 4 hrs in order to activate the hydrogen-related donors and to reduce the concentration of recombination centers such as, for example, di-vacancies or oxygen-vacancy complexes. This annealing step can result in a broadening of the donor peaks.

Alternate methods to create the profile of the present invention such as implantations through the front of the wafer however may also be possible.

As opposed to proton implantation, another option is a multiple helium implantation in combination with a controlled formation of thermal donors. Furthermore, other dopants such as phosphorus or arsenic are also possible.

The depths of the maxima may be set via an appropriate selection of the acceleration energies for the individual implants and are freely selectable in principle.

Prior art field stop zone dopant profiles often had good short circuit ruggedness but poor leakage current yields for switching, typically where the maximum was located too close to the side away from the base material. The increase in leakage current can be explained by doping inhomogeneities in the implanted region. These doping inhomogeneities are induced by particles adhering on the wafer surface during implantation and, thus, locally reducing the penetration depth of the implanted ions. Other known dopant profiles may have had good leakage current yields, but had poor short circuit ruggedness, typically where the doping maximum was located further away from the side away from the base material.

The present profile advantageously provides for excellent short-circuit ruggedness of the IGBT. Holes are delivered from the p emitter 28, and the holes partly compensate for a negative space charge on the anode side, so that the electric field gradient, and thus the maximum electric field intensity, does not assume excessively high values near the anode contact 14 when the electric field is switched over during short-circuit operation. Increased hole injection may be achieved since dopant maximum 52 has a lower dopant concentration than dopant maximum 54. This relationship also reduces the current-dependence of the emitter efficiency of the anode-side pn junction in the IGBT. For a soft decay of the current in the end phase of the switching response during turn off, the present profile also advantageously raises the charge carrier concentration between the side 30 and the second maximum 54. A sufficient amount of charge carriers in this area is available even during the end phase of the reverse recovery phase, so that the dI/dt (change in current with respect to change in time) gradient of current decay is sufficiently low and excessive overvoltages across parasitic inductivities are avoided.

Another advantage of the profile 34 is that the leakage current yield can be substantially improved. Using higher implantation energies, the radiation passes through even larger particles located on the semiconductor surface during the implantation process. A higher dopant concentration in the second implant compared to the first implant therefore delivers a better leakage current yield than in the reverse case.

P emitter 28 may be a shallow profile emitter. However, emitter variants may include, for example, thermally diffused p-emitters or p-emitters manufactured by laser annealing or emitters manufactured by a combination of these methods. In particular, annealed emitters have the advantage of a greater lateral homogeneity. Emitters manufactured in this way are characterized by higher emitting efficiency which may be further adjusted via a field stop profile according to the present invention, so that leakage currents and switching loss at nominal current and lower currents are reduced. In contrast, in the event of a short circuit, the profile has almost no effect on the emitter efficiency due to the high charge carrier concentration, as is desired.

FIG. 3 shows schematically a further possible field stop zone dopant profile 134 according to another embodiment of the present invention. Three implants 62, 64, 66 with dopant concentration maxima 72, 74, 76 may be provided. Implant 62 may be created for example via a proton implantation at 800 keV, implant 64 via a proton implantation at 1200 keV and implant 66 via a proton implantation at 1500 keV. The dopant concentration maxima depths are about 11, 20 and 30 micrometers for these energies and the concentration maxima may be 2E15, 2E14 and 5E14/cubic centimeter, respectively, for example. The dip in the second concentration maximum 74 may be advantageous for turning off properties. Thus, according to another embodiment of the present invention the second dopant concentration maximum, for example dopant concentration maximum 74, has a concentration at least 10 percent smaller than either of a first or third dopant concentration maximum between which the second dopant concentration maximum is located, for example dopant concentration maximum 72 and dopant concentration maximum 76.

FIG. 4 shows schematically a diode 110 having for example an anode contact 114 and a cathode contact 112, as well as a p emitter 122, an n+ emitter 127 and n− base 124 forming a pn junction with p-emitter 122. A field stop zone 126 for example having the profile 134 may also be provided. Diode 110 may be formed using thin film technology as with the IGBT, and the formation of the field stop zone 126 may be similar to that for the IGBT.

While the field stop zone profile has been described with n channel devices, it may also be used with p channel type devices.

Strack, Helmut, Pfirsch, Frank, Schulze, Hans-Joachim, Niedernostheide, Franz-Josef, Schaeffer, Carsten

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9953974, Dec 09 2011 MIE FUJITSU SEMICONDUCTOR LIMITED Tipless transistors, short-tip transistors, and methods and circuits therefor
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Patent Priority Assignee Title
5006477, Nov 25 1988 Hughes Aircraft Company Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices
6482681, May 05 2000 Infineon Technologies Americas Corp Hydrogen implant for buffer zone of punch-through non epi IGBT
6559023, Feb 09 2001 FUJI ELECTRIC CO , LTD Method of fabricating a semiconductor device with phosphorous and boron ion implantation, and by annealing to control impurity concentration thereof
6696705, Jan 12 2000 INFINEON TECHNOLOGIES BIPOLAR GMBH & CO KG Power semiconductor component having a mesa edge termination
6707111, May 05 2000 Infineon Technologies Americas Corp Hydrogen implant for buffer zone of punch-through non EPI IGBT
6770917, Sep 22 2000 Infineon Technologies AG; EUPEC EUROPAISCHE GESELLSCHAFT FUR LEISTUNGSHALB-LEITER MBH & CO KG High-voltage diode
6924177, Mar 02 1999 Infineon Technologies AG Method for producing a thyristor
7005761, May 19 2000 Infineon Technologies AG Circuit configuration for off-load switching, switch mode power supply, clocked supply, voltage regulator, lamp switch, and methods for operating the circuit configuration
20020190281,
20050164476,
20050215042,
20060081923,
DE3339393,
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