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The ornamental design for a "semiconductor device", as shown and described.
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FIG. 1 is a top, front and right side perspective view of a semiconductor device according to my design;
FIG. 2 is a front elevational view thereof;
FIG. 3 is a rear elevational view thereof;
FIG. 4 is a top plan view thereof;
FIG. 5 is a bottom plan view thereof;
FIG. 6 is a right side elevational view thereof, the left side elevational view being a mirror image thereof;
FIG. 7 is a view of a further embodiment of a semiconductor device similar to FIG. 1, the broken lines illustrating environmental structure of this embodiment which does not form part of the design of this embodiment;
FIG. 8 is a front elevational view thereof;
FIG. 9 is a rear elevational view thereof;
FIG. 10 is a top plan view thereof;
FIG. 11 is a bottom plan view thereof; and,
FIG. 12 is a right side elevational view thereof, the left side elevational view being a mirror image thereof.
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Mar 06 2002 | Sharp Kabushiki Kaisha | (assignment on the face of the patent) | / | |||
Mar 20 2002 | KOIZUMI, HIDESHI | Sharp Kabushiki Kaisha | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 012898 | /0683 |
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