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The ornamental design for a semiconductor carrier, as shown and described.
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FIG. 1 is a top plan view of a semiconductor carrier of our new design in its entirety;
FIG. 2 is a bottom plan view of our new design;
FIG. 3 is a right end view of our new design;
FIG. 4 is a left end view of our new design;
FIG. 5 is a front view of our new design;
FIG. 6 is a rear view our new design; and,
FIG. 7 is a left, front perspective view of our new design.
Matsuoka, Noriyuki, Hisaishi, Minoru, Suzuki, Takeyuki
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| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Jul 26 2004 | HISAISHI, MINORU | YAMAICHI ELECTRONICS CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 015628 | /0993 | |
| Jul 26 2004 | MATSUOKA, NORIYUKI | YAMAICHI ELECTRONICS CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 015628 | /0993 | |
| Jul 26 2004 | SUZUKI, TAKEYUKI | YAMAICHI ELECTRONICS CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 015628 | /0993 | |
| Jul 27 2004 | Yamaichi Electronics Co., Ltd. | (assignment on the face of the patent) | / |
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