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The ornamental design for a semiconductor device, as shown and described.
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FIG. 1 is a front, top and right side perspective view of a semiconductor device, showing our new design;
FIG. 2 is a front elevational view thereof; the opposite side being a mirror image thereof;
FIG. 3 is a right side elevational view thereof; the opposite side being a mirror image thereof;
FIG. 4 is a top plan view thereof; and,
FIG. 5 is a bottom plan view thereof.
Kamidoi, Hiroshi, Ishihara, Toshiya
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Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jan 15 2004 | KAMIDOI, HIROSHI | Kabushiki Kaisha Toshiba | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 015030 | /0423 | |
Jan 15 2004 | ISHIHARA, TOSHIYA | Kabushiki Kaisha Toshiba | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 015030 | /0423 | |
Feb 27 2004 | Kabushiki Kaisha Toshiba | (assignment on the face of the patent) | / |
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