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The ornamental design for a semiconductor device, as shown and described.
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FIG. 1 is a front perspective view of a semiconductor device, showing our new design;
FIG. 2 is a rear perspective view thereof;
FIG. 3 is a top plan view thereof; a bottom plan view being a mirror image thereof;
FIG. 4 is a right side elevational view thereof; a left side elevational view being a mirror image thereof;
FIG. 5 is a front elevational view thereof;
FIG. 6 is a rear elevational view thereof;
FIG. 7 is a front perspective view of a second embodiment of a semiconductor device, showing our new design;
FIG. 8 is a rear perspective view thereof;
FIG. 9 is a top plan view thereof; a bottom plan view being a mirror image thereof;
FIG. 10 is a right side elevational view thereof; a left side elevational view being a mirror image thereof;
FIG. 11 is a front elevational view thereof; and,
FIG. 12 is a rear elevational view thereof.
Yoshihira, Takayuki, Ookura, Gentaro
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Aug 12 2002 | YOSHIHIRA, TAKAYUKI | Kabushiki Kaisha Toshiba | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 013336 | /0589 | |
Aug 12 2002 | OOKURA, GENTARO | Kabushiki Kaisha Toshiba | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 013336 | /0589 | |
Sep 27 2002 | Kabushiki Kaisha Toshiba | (assignment on the face of the patent) | / |
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