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Patent
   D639755
Priority
Jan 20 2010
Filed
Jan 20 2010
Issued
Jun 14 2011
Expiry
Jun 14 2025
Inventors
Root, Brya…
Assg.orig
Celadon Sy…
Assg.curr
CELADON SY…
Entity
unknown
Referenced by
7
References
15
Maint.:
n/a
The ornamental design for a top contact layout board in an electrical system, as shown and described.

FIG. 1 is a top plan view of the top contact layout board for an electrical system showing the claimed design as flat and two-dimensional, illustrating our new design;

FIG. 2 is a side view, all other side views being a mirror image thereof; and,

FIG. 3 s a bottom plan view.

The broken lines showing of a motherboard is for illustrative purposes only and forms no part of the claimed design.
INVENTORS:

Root, Bryan J., Funk, William A.

THIS PATENT IS REFERENCED BY THESE PATENTS:
Patent Priority Assignee Title
D654033, Jan 20 2010 CELADON SYSTEMS, INC Grooved wire support for a probe test core
D691974, Dec 22 2011 Tokyo Electron Limited Holding pad for transferring a wafer
D693319, Dec 22 2011 Tokyo Electron Limited Holding pad for transferring a wafer
D713363, Dec 31 2013 CELADON SYSTEMS, INC Support for a probe test core
D722031, Dec 31 2013 CELADON SYSTEMS, INC Top contact layout board in an electrical system
D770404, Aug 05 2015 WiTricity Corporation Resonator coil
D873782, May 17 2016 Electro Scientific Industries, Inc Component carrier plate
THIS PATENT REFERENCES THESE PATENTS:
Patent Priority Assignee Title
3795845,
4495377, Dec 30 1982 International Business Machines Corporation Substrate wiring patterns for connecting to integrated-circuit chips
5091822, Jun 15 1989 Graphico Co., Ltd. Radial type of parallel system bus structure with printed, twisted conductor lines
5210682, Oct 19 1990 Graphico Co., Ltd. Radial type of parallel system bus structure having pairs of conductor lines with impedance matching elements
5491364, Aug 31 1994 Delphi Technologies, Inc Reduced stress terminal pattern for integrated circuit devices and packages
6160716, Sep 08 1997 Rambus Inc Motherboard having one-between trace connections for connectors
6310398, Dec 03 1998 Walter M., Katz Routable high-density interfaces for integrated circuit devices
6556454, Oct 31 2000 III Holdings 1, LLC High density contact arrangement
6664620, Jun 29 1999 Intel Corporation Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer
6793500, Sep 18 2003 International Business Machines Corporation Radial contact pad footprint and wiring for electrical components
7808110, Feb 01 2007 Siliconware Precision Industries Co., Ltd. Semiconductor package substrate
20020060318,
225434,
D320361, Jun 02 1989 Tokyo Electron Limited Wafer probe plate holder
D552048, Oct 26 2005 Hon Hai Precision Industry Co., Ltd. Printed circuit board
ASSIGNMENT RECORDS    Assignment records on the USPTO
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Executed onAssignorAssigneeConveyanceFrameReelDoc
Jan 20 2010Celadon Systems, Inc.(assignment on the face of the patent)
Mar 30 2010ROOT, BRYAN J CELADON SYSTEMS, INC ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0241720891 pdf
Mar 30 2010FUNK, WILLIAM A CELADON SYSTEMS, INC ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0241720891 pdf
Nov 25 2015CELADON SYSTEMS, INC CELADON SYSTEMS, INC CHANGE OF ADDRESS0419120980 pdf
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