Configurable electrical circuit having configurable logic elements and configurable interconnects

Abstract

A configurable logic array comprises a plurality of configurable logic elements variably interconnected in response to control signals to perform a selected logic function. Each configurable logic element in the array is in itself capable of performing any one of a plurality of logic functions depending upon the control information placed in the configurable logic element. Each configurable logic element can have its function varied even after it is installed in a system by changing the control information placed in that element. structure is provided for storing control information and providing access to the stored control information to allow each configurable logic element to be properly configured prior to the initiation of operation of the system of which the array is a part. Novel interconnection structures are provided to facilitate the configuring of each logic element.

Description

This 4B,salve slave CLAs 1 to N. In this sense, the structure of FIG. 8B is self-configuring in response to power on or a reset signal.

A single board microcomputer using a Configurable Logic Array of this invention is shown in FIG. 11. Configurable Logic Array 110 performs the chip decode functions, the latching functions and the various special logic that is necessary to implement a single board microcomputer. The CLA has an output lead ("DONE") which is low from the time the power is turned on until the single board microcomputer is fully functional.

The first event that occurs when power is turned on is that the Configurable Logic Array 110 forces the Z8002 CPU 111 into the reset state. Reset forces the outputs of the CPU to be tri-stated (i.e., to go to high impedance level) which makes it possible for the Configurable Logic Array to use the control lines from the CPU 111 while it is being configured. The Configurable Logic Array 110 through a set of address lines (LA₁ -LA₁2) addresses the EPROMS 113 which are also used for the bootstrap of the Z8002 CPU 111. In addition, the EPROMS 113 have available in them configuration information for the CLA 110. The CLA 110 has signals which, during the self-loading time, are fixed so that particular bi-directional buffers 112 can be set in the correct direction for loading data from the EPROMS 113 to the Configurable Logic Array 110. Configurable Logic Array 110 then sequentially addresses locations in the EPROMS 113 which are read into the Configurable Logic Array 110 to configure the CLA 110. When array 110 is totally configured it then takes on its new functions and unlatches the DONE output which releases the reset line to the CPU 111. CPU 111 is then in control of the entire system. The decode used herein decodes the addresses from the CPU to create chip enables and chip selects for the various RAMS and EPROMS in the system and for the I/O devices as well.

The bi-directional selectable buffer 112 shown in FIG. 11 is illustrated in more detail in FIGS. 10A and 10B. FIG. 10A shows the bi-directional buffer as comprising an inverter 101 connected into a CMOS inverter comprising p-channel transistor 103 and n-channel transistor 104, the output lead of which is gated by pass transistor 108. In the other direction, inverter 102 feeds an input signal onto the gates of p-channel pass transistor 105 connected in series with n-channel transistor 106. The output from the node between the p- and n-channel transistors is controlled by pass transistor 107. The pass transistors 107 and 108 are activated by the Q, Q signals from the storage element which can comprise a standard flip-flop. Thus, the buffer passes a signal in one direction or the other on leads 109a or 109b, depending upon whether or not pass transistor 107 or pass transistor 108 is turned on.

FIG. 10B illustrates schematically the circuit of FIG. 10A. In FIG. 10B, the series connected p-channel and n-channel transistors 103 and 104 have been represented by inverter 103' and series connected p-channel pass transistor 105 and n-channel pass transistor 106 have been represented by invertor inverter 105'. Of course, in operation, the two circuits are identical.

With reference to FIGS. 4A and 4B directional amplifiers (shown by an X in a box) are used to amplify signals which have been attenuated by a number of pass transistors. This speeds up considerably the operation of the circuit. The delay of a signal increases approximately in proportion to the square of the number of pass transistors through which a signal must pass. The amplifier brings the signal voltage back to its normal level.

In view of the above description, it will be obvious to those skilled in the art that a configurable logic element in a Configurable Logic Array is capable of being reconfigured even after the Configurable Logic Array has been installed in a circuit. Indeed, this is one of the key advantages of the Configurable Logic Array of this invention. Thus, a Configurable Logic Array can be reconfigured to provide a new logical function as part of its normal operation in the system of which it is a part.

Another advantage of this invention is that the I/O pads can be used as either input or output pads and can be controlled by any internal signal using pass transistors.

While one embodiment of this invention has been described, other embodiments of this invention will be obvious in view of the above disclosure.

Claims

1. An interconnect structure for programmably interconnecting lines within an integrated circuit comprising:

at least three sets of interconnect lines including a first set, a second set, and a third set;

programmable means, not including said sets of interconnect lines, for connecting at least one of said lines in said first set to at least one of said lines in said second set, for connecting at least one of said lines in said first set to at least one of said lines in said third set, and for connecting at least one of said lines in said second set to at least one of said lines in said third set.

2. An array of interconnect structures, each said interconnect structure as in claim 1, and each interconnect structure in said array having its own selected number of interconnect lines and its own programmable means for connecting interconnect lines in its own first, second and third sets.

3. An interconnect structure as in claim 1 in which

said first set comprises two lines; and

said programmable means comprises

means for connecting each of said two lines in said first set to at least one line in said second set and

means for connecting each of said two lines in said first set to said at least one line in said third set.

4. An array of interconnect structures, each said interconnect structure as in claim 3, and each interconnect structure in said array having its own selected number of interconnect lines and its own programmable means for connecting interconnect lines in its own first, second and third sets.

5. An interconnect structure as in claim 3 in which

said second set comprises two lines, and

said third set comprises two lines; and

said programmable means comprises

means for connecting each of said two lines in said first set to each of said two lines in said second set,

means for connecting each of said two lines in said first set to each of said two lines in said third set, and

means for connecting each of said two lines in said second set to each of said two lines in said third set.

6. An array of interconnect structures, each said interconnect structure as in claim 5, and each interconnect structure in said array having its own selected number of interconnect lines and its own programmable means for connecting interconnect lines in its own first, second and third sets.

7. An interconnect structure as in claim 5 in which said at least three sets of interconnect lines includes a fourth set, and said interconnect structure further comprises:

programmable means for connecting at least one of said lines in said fourth set to at least one of said lines in said first, second and third sets.

8. An array of interconnect structures, each said interconnect structure as in claim 7, and each interconnect structure in said array having its own selected number of interconnect lines and its own programmable means for connecting interconnect lines in its own first, second, third and fourth sets.

9. An interconnect structure as in claim 7 in which said programmable means for connecting at least one of said lines in said first, second, third, and fourth sets comprises programmable means for connecting said two lines in said first set to each of said two lines in said second set, for connecting said two lines in said first set to each of said two lines in said third set, for connecting said two lines in said first set to each of two lines in said fourth set, for connecting said two lines in said second set to each of said two lines in said third set, for connecting said two lines in said second set to each of said two lines in said fourth set, and for connecting said two lines in said third set to each of said two lines in said fourth set.

10. An array of interconnect structures, each said interconnect structure as in claim 9, and each interconnect structure in said array having its own selected number of interconnect lines and its own programmable means for connecting.

11. A configurable system comprising:

one master configurable logic array;

a plurality of slave configurable logic arrays;

at least one memory;

said master configurable logic array having

means for retrieving data from said at least one memory,

means for first using said data for configuring itself, and

means for passing some of said data to said plurality of slave configurable logic arrays.

12. A configurable system as in claim 11 in which said means for retrieving data from said at least one memory includes

means for addressing said memory cells in said at least one memory, and

means for transferring selected data from said at least one memory to said master configurable logic array.

13. A configurable system as in claim 11 in which said plurality of slave configurable logic arrays include

means for being configured and

means for receiving and passing said data from said master configurable logic array to said plurality of slave configurable logic arrays whereby each of said slave configurable logic arrays is programmed according to said data in said at least one memory.

14. A configurable system as in claim 11 in which said means for passing some of said data to said plurality of slave configurable logic arrays comprises

means for passing said data through said plurality of slave configurable logic arrays sequentially by means of a shift register controlled by clock signals provided by said master configurable logic array.

15. A configurable system comprising:

a master configurable logic array;

a plurality of slave configurable logic arrays; and

a controller including

means for addressing said configurable logic arrays and

means for sending data to said configurable logic arrays; wherein said master configurable logic array includes

means for being configured by said data from said controller and

means for configuring said slave configurable logic arrays.

16. A configurable system as in claim 15 in which said slave configurable logic arrays include means for being configured and means for receiving and passing said data from said master configurable logic array.

17. A configurable system as in claim 15 in which said means for addressing further includes means for controlling sending said data from said means for sending data.

18. A configurable system as in claim 15 in which said means for configuring said slave configurable logic arrays comprises means for receiving data from said controller, means for passing some of said data to said slave configurable logic arrays and means for controlling the passing of said data to said slave configurable logic arrays.

19. A configurable system as in claim 15 in which said means for being configured of said master configurable logic array comprises means for receiving configuration control bits from said controller, and said means for configuring said slave configurable logic arrays comprises means for passing said data through said plurality of slave configurable logic arrays sequentially by means of a shift register as controlled by clock signals provided by said master configurable logic array.

20. A configurable system as in claim 11 wherein said memory is nonvolatile.

21. A programmable circuit comprising:

a plurality of configurable logic elements, each configurable logic element having a plurality of input leads and at least one output lead and having a programming means to cause said configurable logic element to perform a selected logic function;

a plurality of input/output ports;

a group of interconnect lines;

means for programmably connecting each of said input leads of each of said configurable logic elements to at least one of said interconnect lines;

means for programmably connecting said at least one output lead of each of said configurable logic elements to at least one of said interconnect lines;

means for programmably connecting each of said input/output ports to at least one of said interconnect lines; and

means for programmably connecting each one of said interconnect lines to at least one other of said interconnect lines;

whereby each of said input leads and each of said at least one output lead of each of said configurable logic elements can be connected directly or indirectly to each of said input/output ports and to each other, and whereby each of said configurable logic elements can be programmed to perform a selected one of a plurality of logic functions, and said configurable logic elements can be connected to each other and to said input/output ports in a selectable manner.

22. A programmable circuit as in claim 21 wherein said programming means of each of said configurable logic elements comprises logic element pass transistors.

23. A programmable circuit as in claim 22 wherein said programming means includes a plurality of memory cells and wherein each of said logic element pass transistors is controlled by a corresponding one of said plurality of memory cells.

24. A programmable circuit as in claim 23 in which said plurality of memory cells forms at least part of a shift register, control signals being loaded into said memory cells by being transferred through said shift register until each of said signals is properly located in said corresponding one of said memory cells.

25. A programmable circuit as in claim 23 in which said memory cells can be re-programmed.

26. A programmable circuit as in claim 21 in which each of said interconnect lines is capable of being connected directly or indirectly to one or more of the other of said interconnect lines, to one or more of said input/output ports, to one or more of said input leads and to one or more of said output leads, thereby allowing a user to connect said leads and lines together as desired.

27. A programmable interconnect circuit as in claim 21 wherein said means for programmably connecting each of said input leads of each of said configurable logic elements to at least one of said interconnect lines, said means for programmably connecting said at least one output lead of each of said configurable logic elements to at least one of said interconnect lines, said means for programmably connecting each of said input/output ports to at least one of said interconnect lines, and said means for programmably connecting each of said interconnect lines to at least one other of said interconnect lines comprise pass transistors.

28. A programmable circuit as in claim 27

wherein said means for programmably connecting further comprises memory means, said memory cells forming at least part of a shift register,

wherein each of said pass transistors is controlled by one of said memory cells, and

wherein said means for programmably connecting further comprises means for transferring said series of signals through said shift register until each of said signals is properly located in an associated one of said memory cells uniquely coupled to one of said pass transistors.

29. A programmable circuit as in claim 28 in which said means for programmably connecting includes means for changing the contents of said memory cells, thereby to reconfigure said programmable circuit.

30. A programmable circuit comprising:

a plurality of logic elements, each logic element having a plurality of input leads and at least one output lead, and having a programming means to cause said logic element to perform a selected logic function;

a plurality of input/output ports;

a group of interconnect lines;

means for programmably connecting each of said input leads of each of said logic elements to at least one of said interconnect lines;

means for programmably connecting said at least one output lead of each of said logic elements to at least one of said interconnect lines;

means for programmably connecting each of said input/output ports to at least one of said interconnect lines; and

means for programmably connecting each of said interconnect lines to at least one other of said interconnect lines;

whereby each of said logic elements can be programmed to perform a selected one of a plurality of logic functions, and said logic elements can be connected to each other and to said input/output ports in a selectable manner. 31. A programmable circuit as in claim 30 wherein programming means of each of said logic elements comprises transistors. 32. A programmable circuit as in claim 31 wherein said programming means includes a plurality of memory cells and wherein said transistors are controlled by said plurality of memory cells. 33. A programmable circuit as in claim 32 in which said plurality of memory cells forms at least part of a shift register, control signals being loaded into said memory cells by being transferred through said shift register until each of said signals is properly located in said corresponding one of said memory cells. 34. A programmable circuit as in claim 32 in which said memory cells can be re-programmed.

35. A programmable circuit as in claim 30 in which each of said interconnect lines is capable of being connected directly or indirectly to one or more of the other of said interconnect lines, to one or more of said input/output ports, to one or more of said input leads and to one or more of said output leads, thereby allowing a user to connect said leads and lines together as desired. 36. A programmable circuit as in claim 30 wherein said means for programmably connecting comprise transistors. 37. A programmable circuit as in claim 36

wherein said means for programmably connecting further comprise memory cells, said memory cells forming at least part of a shift register,

wherein said transistors are controlled by said memory cells, and

wherein said means for programmably connecting further comprises means for transferring said series of signals through said shift register until each of said signals is properly located in an associated one of said memory cells. 38. A programmable circuit as in claim 37 in which said means for programmably connecting includes means for changing the contents of said memory cells, thereby to reconfigure said programmable circuit. 39. A programmable circuit comprising:

a plurality of logic elements, each logic element having a plurality of input leads and at least one output lead, and having a programming means to cause said logic element to perform a selected logic function;

a group of interconnect lines;

means for programmably connecting each of said input leads of each of said logic elements to at least one of said interconnect lines;

means for programmably connecting said at least one output lead of each of said logic elements to at least one of said interconnect lines; and

means for programmably connecting each of said interconnect lines to at least one other of said interconnect lines;

whereby each of said logic elements can be programmed to perform a selected one of a plurality of logic functions, and said logic elements can be

connected to each other in a selectable manner. 40. A programmable circuit as in claim 39 wherein said programming means of each of said configurable logic elements comprises transistors. 41. A programmable circuit as in claim 40 wherein said programming means includes a plurality of memory cells and wherein said transistors are controlled by said plurality of memory cells. 42. A programmable circuit as in claim 41 in which said plurality of memory cells forms at least part of a shift register, control signals being loaded into said memory cells by being transferred through said shift register until each of said signals is properly located in said corresponding one of said memory cells. 43. A programmable circuit as in claim 41 in which said memory cells can be re-programmed. 44. A programmable circuit as in claim 39 in which each of said interconnect lines is capable of being connected directly or indirectly to one or more of the other of said interconnect lines, to one or more of said input leads and to one or more of said output leads, thereby allowing a user to connect said leads and lines together as desired. 45. A programmable circuit as in claim 39 wherein said means for programmably connecting comprise transistors. 46. A programmable circuit as in claim 45

wherein said means for programmably connecting further comprise memory cells, said memory cells forming at least part of a shift register,

wherein said transistors are controlled by said memory cells, and

wherein said means for programmably connecting further comprises means for transferring said series of signals through said shift register until each of said signals is properly located in an associated one of said memory

cells. 47. A programmable circuit as in claim 46 in which said means for programmably connecting includes means for changing the contents of said memory cells, thereby to reconfigure said programmable circuit. 48. A programmable integrated circuit comprising:

a plurality of logic elements, each logic element having a plurality of input leads and at least one output lead;

a group of interconnect lines;

means for programmably connecting said input and output leads of said logic elements to each other through said interconnect lines; and

programming means responsive to electrical signals for causing said logic elements to perform a selected logic function, and causing said input and output leads of said logic elements to be connected together as desired. 49. A programmable circuit as in claim 48 wherein said programming means of each of said logic elements comprises transistors. 50. A programmable circuit as in claim 49 wherein said programming means includes a plurality of memory cells and wherein said transistors are controlled by said plurality of memory cells. 51. A programmable circuit as in claim 50 in which said plurality of memory cells forms at least part of a shift register, control signals being loaded into said memory cells by being transferred through said shift register until each of said signals is properly located in said corresponding one of said memory cells. 52. A programmable circuit as in claim 50 in which said memory cells can be re-programmed. 53. A programmable circuit as in claim 48 in which each of said interconnect lines is capable of being connected directly or indirectly to one or more of the other of said interconnect lines, to one or more of said input leads and to one or more of said output leads, thereby allowing a user to connect said leads and lines together as desired. 54. A programmable circuit as in claim 48 wherein said means for programmably connecting comprise transistors. 55. A programmable circuit as in claim 54

wherein said means for programmably connecting further comprise memory cells, said memory cells forming at least part of a shift register,

wherein said transistors are controlled by said memory cells, and

wherein said means for programmably connecting further comprises means for transferring said series of signals through said shift register until each of said signals is properly located in an associated one of said memory

cells. 56. A programmable circuit as in claim 55 in which said means for programmably connecting includes means for changing the contents of said memory cells, thereby to reconfigure said programmable circuit. 57. A configurable logic array chip comprising:

a plurality of storage cells for holding configuration information, said configuration information configuring said configurable logic array chip; and

means for causing said configuration information to be loaded into said storage cells from a device external to said configurable logic array chip. 58. A configurable logic array chip as in claim 57 in which said means for causing said configuration information to be loaded causes said configuration information to be loaded in response to said system being powered up. 59. A configurable logic array chip as in claim 57 in which said means for causing said configuration information to be loaded causes said configuration information to be loaded in response to said system being reset. 60. A system comprising:

said configurable logic array chip as in claim 57; and

said device external to said configurable logic array chip. 61. A system as in claim 60 in which said means for storing said configuration information comprises a nonvolatile memory device. 62. A system as in claim 61 further including means for loading said configuration information into said configurable logic array chip as a serial bit stream. 63. A system as in claim 61 further including means for loading said configuration information into said configurable logic array chip in parallel. 64. A system comprising a configurable logic array chip as in claim 57 and further comprising second means not part of said configurable logic array chip for causing said configuration information to be loaded into said storage cells. 65. A system as in claim 64 in which said second means comprises a microprocessor. 66. A system as in claim 65 further comprising said device external to said configurable logic array chip. 67. A system as in claim 66 in which said means for storing said configuration information comprises a nonvolatile memory. 68. A system as in claim 65 in which said microprocessor provides control, address, and data information to said configurable logic array chip. 69. A system comprising a first configurable logic array chip as in claim 57 and further comprising:

a second configurable logic array chip comprising means for holding information in storage cells, said information in said storage cells configuring said second configurable logic array chip; and

means for passing configuration information from said first configurable logic array chip to said second configurable logic array chip.

70. A system as in claim 69 in which said means for passing comprises a shift register. 71. A system comprising:

a first configurable logic array chip;

means for loading configuration information into said first configurable logic array chip;

said first configurable logic array chip including means for loading configuration information into a second configurable logic array chip. 72. A system as in claim 71 in which said means for loading configuration information into said first configurable logic array chip is a microprocessor. 73. A system as in claim 72 in which said microprocessor has access to a storage device for holding said configuration information. 74. A system as in claim 71 in which said means for loading configuration information into said first configurable logic array chip is a third configurable logic array chip. 75. A system as in claim 71 further comprising said second configurable logic array chip connected so as to receive said configuration information from said first configurable logic array chip. 76. A system as in claim 73 in which said first and second configurable logic array chips include means for being configured by said configuration information. 77. In a system having a configurable logic array chip and means for loading configuration information into said configurable logic array chip, and means for operating said configurable logic array chip, a method for configuring said configurable logic array chip comprising the steps of:

connecting to said configurable logic array chip means for taking data from a supplier of configuration information;

disabling said means for operating said configurable logic array chip;

taking said information from said supplier of information; and

enabling said means for operating said configurable logic array chip. 78. A method for configuring as in claim 77 comprising the further step, performed between disabling and enabling said means for operating, of passing some of said information from said configurable logic array chip to another configurable logic array chip. 79. A method for configuring as in claim 77 in which said step of connecting a means for taking said information from said supplier of configuration information comprises connecting leads from said configurable logic array chip to means for controlling direction on a line such that initial direction of said line is established for allowing data to flow from said supplier of information to said configurable logic array

chip. 80. A method for configuring as in claim 77 in which said step of taking said information from said supplier of information comprises sequentially addressing said supplier of information with a counter which is part of said configurable logic array chip. 81. A configurable system comprising:

one master configurable logic array;

at least one slave configurable logic array;

at least one memory;

said master configurable logic array having

means for retrieving data from said at least one memory,

means for first using said data for configuring itself, and

means for passing some of said data to said at least one slave configurable logic array. 82. A configurable system as in claim 81 in which said means for retrieving data from said at least one memory includes

means for addressing memory cells in said at least one memory, and

means for transferring selected data from said at least one memory to said

master configurable logic array. 83. A configurable system as in claim 81 in which said at least one slave configurable logic array includes

means for being configured and

means for receiving and passing said data from said master configurable logic array to said at least one slave configurable logic array whereby each of said at least one slave configurable logic array is programmed according to said data in said at least one memory. 84. A configurable system as in claim 81 in which said means for passing some of said data to said at least one slave configurable logic array comprises

means for passing said data through said at least one slave configurable logic array sequentially by means of a shift register controlled by clock signals provided by said master configurable logic array. 85. A configurable system as in claim 81 wherein said memory is nonvolatile. 86. A configurable system comprising:

a master configurable logic array;

at least one slave configurable logic array; and a controller including

means for addressing said configurable logic arrays and

means for sending data to said configurable logic arrays;

wherein said master configurable logic array includes

means for being configured by said data from said controller and

means for configuring said at least one slave configurable logic array. 87. A configurable system as in claim 86 in which said at least one slave configurable logic array includes means for being configured and means for receiving and passing said data from said master

configurable logic array. 88. A configurable system as in claim 86 in which said means for addressing further includes means for controlling sending said data from said means for sensing data. 89. A configurable system as in claim 86 in which said means for configuring said at least one slave configurable logic array comprises means for receiving data from said controller, means for passing some of said data to said at least one slave configurable logic array, and means for controlling the passing of said data to said at least one slave configurable logic array. 90. A configurable system as in claim 86 in which said means for being configured of said master configurable logic array comprises means for receiving configuration control bits from said controller, and said means for configuring said at least one slave configurable logic array comprises means for passing said data through said at least one slave configurable logic array sequentially by means of a shift register as controlled by clock signals provided by said master configurable logic array. 91. An interconnect structure for programmably interconnecting lines within an integrated circuit comprising:

at least three sets of interconnect lines including a first set, a second set, and a third set;

programmable means for connecting at least one of said lines in said first set to at least one of said lines in said second set, for connecting at least one of said lines in said first set to at least one of said lines in said third set, and for connecting at least one of said lines in said second set to at least one of said lines in said third set, each pair of said lines being connectable by a single programmable means. 92. An interconnect structure for programmably interconnecting lines within an integrated circuit comprising:

at least three sets of interconnect lines including a first set, a second set, and a third set;

first programmable means for connecting at least one of said lines in said first set to at least one of said lines in said second set, second programmable means for connecting at least one of said lines in said first set to at least one of said lines in said third set, and third programmable means for connecting at least one of said lines in said second set to at least one of said lines in said third set, said first, second, and third programmable means being controllable independent of each other. 93. An interconnect structure for programmably interconnecting lines within an integrated circuit comprising:

at least three sets of interconnect lines including a first set, a second set, and a third set;

first programmable means for connecting at least one of said lines in said first set to at least one of said lines in said second set, second programmable means for connecting at least one of said lines in said first set to at least one of said lines in said third set, and third programmable means for connecting at least one of said lines in said second set to at least one of said lines in said third set, said first, second, and third programmable means being connected such that a signal can pass between any two of said at least one of said lines in said first, second, and third sets through only a single means for connecting. 94. An array of interconnect structures, each said interconnect structure as in claim 91, 92 or 93, and each interconnect structure in said array having its own selected number of interconnect lines and its own programmable means for connecting interconnect lines in its own first, second and third sets. 95. An interconnect structure as in claim 91, 92, or 93 in which said first set comprises two lines; and said programmable means comprises

means for connecting each of said two lines in said first set to at least one line in said second set and

means for connecting each of said two lines in said first set to said at least one line in said third set. 96. An array of interconnect structures, each said interconnect structure as in claim 95, and each interconnect structure in said array having its own selected number of interconnect lines and its own programmable means for connecting interconnect lines in its own first, second and third sets. 97. An interconnect structure as in claim 95 in which said second set comprises two lines, and said third set comprises two lines; and said programmable means comprises

means for connecting each of said two lines in said first set to each of said two lines in said second set,

means for connecting each of said two lines in said first set to each of said two lines in said third set, and

means for connecting each of said two lines in said second set to each of said two lines in said third set. 98. An array of interconnect structures, each said interconnect structure as in claim 97, and each interconnect structure in said array having its own selected number of interconnect lines and its own programmable means for connecting interconnect lines in its own first, second and third sets. 99. An interconnect structure as in claim 97 in which said at least three sets of interconnect lines includes a fourth set, and said interconnect structure further comprises:

programmable means for connecting at least one of said lines in said fourth set to at least one of said lines in said first, second and third sets. 100. An array of interconnect structures, each said interconnect structure as in claim 99, and each interconnect structure in said array having its own selected number of interconnect lines and its own programmable means for connecting interconnect lines in its own first, second, third and fourth sets. 101. An interconnect structure as in claim 99 in which said programmable means for connecting at least one of said lines in said first, second, third, and fourth sets comprises programmable means for connecting said two lines in said first set to each of said two lines in said second set, for connecting said two lines in said first set to each of said two lines in said third set, for connecting said two lines in said first set to each of two lines in said fourth set, for connecting said two lines in said second set to each of said two lines in said third set, for connecting said two lines in said second set to each of said two lines in said fourth set, and for connecting said two lines in said third set to each of said two lines in said fourth set. 102. An array of interconnect structures, each said interconnect structure as in claim 101, and each interconnect structure in said array having its own selected number of interconnect

lines and its own programmable means for connecting. 103. A programmable circuit comprising:

a plurality of logic elements, each logic element having a plurality of input leads for receiving input signals and at least one output lead, each said logic element being configurable to perform a selected logic function to said input signals, and providing said logic function as an output signal on said output lead;

a group of interconnect lines;

programming means responsive to electrical signals for connecting selected ones of said input and output leads of said logic elements to each other through said interconnect lines and causing said logic elements to perform a selected logic function. 104. structure of claim 103 wherein said logic elements can be programmed to perform logic functions on said input signals asynchronously. 105. structure of claim 103 wherein said logic elements can be programmed to provide said output signal on said interconnect lines asynchronously.