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The ornamental design for a semiconductor wafer measuring instrument, as shown and described. |
FIG. 1 is a top, front and right side perspective view of a semiconductor wafer measuring instrument showing my new design;
FIG. 2 is a front elevational view;
FIG. 3 is a right side elevational view, the left side elevational view being a mirror image;
FIG. 4 is a top plan view;
FIG. 5 is a rear elevational view; and
FIG. 6 is a bottom plan view thereof.
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Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Apr 05 1989 | TAKAO, ITARU | TOKYO ELECTRON LIMITED A CORP OF JAPAN | ASSIGNMENT OF ASSIGNORS INTEREST | 005872 | /0746 | |
Apr 25 1989 | Tokyo Electron Limited | (assignment on the face of the patent) | / |
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