Semiconductor wafer testing apparatus

Abstract

Description

FIG. 1 is a top, front and right side perspective view of a semiconductor wafer testing apparatus showing my new design;

FIG. 2 is a top plan view;

FIG. 3 is a front elevational view;

FIG. 4 is a left side elevational view;

FIG. 5 is a right side elevational view;

FIG. 6 is a rear elevational view; and,

FIG. 7 is a bottom plan view thereof.

Claims

The ornamental design for semiconductor wafer testing apparatus, as shown and described.