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The ornamental design for a semiconductor package, as shown and described. |
FIG. 1 is a perspective view of a semiconductor package showing our new design;
FIG. 2 is a top plan view thereof;
FIG. 3 is a left side elevational view thereof;
FIG. 4 is a front elevational view thereof;
FIG. 5 is a bottom plan view thereof;
FIG. 6 is a right side elevational view thereof;
FIG. 7 is a rear elevational view thereof;
FIG. 8 is a perspective view of another embodiment of a semiconductor package showing our new design; and,
FIG. 9 is a front elevational view of the embodiment of FIG. 8. The rest of views of the embodiment of FIG. 8 are the same as those of the embodiment of FIG. 1.
Ueda, Kazuhiko, Takagi, Yuichi
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Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jan 27 1997 | TAKAGI, YUICHI | Sony Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 008655 | /0824 | |
Jan 28 1997 | UEDA, KAZUHIKO | Sony Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 008655 | /0824 | |
Jan 30 1997 | Sony Corporation | (assignment on the face of the patent) | / |
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