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The ornamental design for a wafer level burn-in tester, as shown and described. |
FIG. 1 is a perspective view of the top, front and right side of a wafer level burn-in tester showing our new design;
FIG. 2 is a front view thereof;
FIG. 3 is a right side view thereof;
FIG. 4 is a top plan view thereof;
FIG. 5 is a bottom view thereof; and,
FIG. 6 is a rear view thereof.
Asai, Yoshihiko, Ezawa, Yoshikazu
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Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Nov 17 1999 | ASAI, YOSHIHIKO | MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 010409 | /0480 | |
Nov 17 1999 | EZAWA, YOSHIKAZU | MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 010409 | /0480 | |
Nov 29 1999 | Matsushita Electric Industrial Co., Ltd. | (assignment on the face of the patent) | / |
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