Patent
   D443253
Priority
Jul 14 1999
Filed
Jan 13 2000
Issued
Jun 05 2001
Expiry
Jun 05 2015
Assg.orig
Entity
unknown
5
5
n/a
The ornamental design for a transistor substrate, as shown and described.

FIG. 1 is a front elevational view showing a transistor substrate according to a first embodiment of the present invention;

FIG. 2 is a rear elevational view of the substrate of FIG. 1;

FIG. 3 is a top plan view of the substrate of FIG. 1;

FIG. 4 is a bottom plan view of the substrate of FIG. 1;

FIG. 5 is a right side elevational view of the substrate of FIG. 1, the left side elevational view being a mirror image of the right side elevational view;

FIG. 6 is a top front perspective view of the substrate of FIG. 1;

FIG. 7 is a top plan view showing a transistor substrate according to a second embodiment of the present invention, wherein the front elevational view, the rear elevational view, the bottom plan view, the right side elevational view and the left side elevational view are identical with those of the first embodiment;

FIG. 8 is a top front perspective view of the substrate of FIG. 7;

FIG. 9 is a top plan view showing a transistor substrate according to a third embodiment of the present invention, wherein the front elevational view, the rear elevational view, the bottom plan view, the right side elevational view and the left side elevational view are identical with those of the first embodiment;

FIG. 10 is a top front perspective view of the substrate of FIG. 9;

FIG. 11 is a top plan view showing a transistor substrate according to a fourth embodiment of the present invention, wherein the front elevational view, the rear elevational view, the bottom plan view, the right side elevational view and the left side elevational view are identical with those of the first embodiment; and,

FIG. 12 is a top front perspective view of the substrate of FIG. 11.

Nagase, Toshiaki, Ishikawa, Jun

Patent Priority Assignee Title
D848384, Aug 17 2017 EPISTAR CORPORATION Transistor
ER1445,
ER3604,
ER383,
ER6265,
Patent Priority Assignee Title
5156983, Oct 26 1989 HEWLETT-PACKARD DEVELOPMENT COMPANY, L P Method of manufacturing tape automated bonding semiconductor package
D318271, Jul 04 1987 IBIDEN CO , LTD Substrate for mounting semiconductors
D319629, Apr 13 1988 IBIDEN CO , LTD , A JAPANESE CORP Semiconductor substrate with conducting pattern
D350942, Aug 25 1992 Particle Solutions Semiconductor wafer support
D426522, Apr 21 1998 Advantest Corporation Contactor for semiconductor IC testers
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Executed onAssignorAssigneeConveyanceFrameReelDoc
Jan 13 2000Kabushiki Kaisha Toyoda Jidoshokki Seisakusho(assignment on the face of the patent)
Mar 22 2000NAGASE, TOSHIAKIKabushiki Kaisha Toyoda Jidoshokki SeisakushoASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0107410384 pdf
Mar 22 2000ISHIKAWA, JUNKabushiki Kaisha Toyoda Jidoshokki SeisakushoASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0107410384 pdf
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