Patent
   D621803
Priority
Jul 16 2008
Filed
Jul 16 2008
Issued
Aug 17 2010
Expiry
Aug 17 2024
Assg.orig
Entity
unknown
31
9
n/a
The ornamental design for a “semiconductor wafer processing tape,” as shown and described.

FIG. 1 is a perspective view showing our new design;

FIG. 2 is a top plan view;

FIG. 3 is a bottom plan view;

FIG. 4 is a left side view;

FIG. 5 is a front side view;

FIG. 6 is a right side view;

FIG. 7 is a cross sectional view at 77 of FIG. 1; and,

FIG. 8 is a cross sectional view at 88 of FIG. 1.

Maruyama, Hiromitsu, Taguchi, Shuzo, Morishima, Yasumasa, Ishiwata, Shinichi

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Executed onAssignorAssigneeConveyanceFrameReelDoc
Jul 16 2008The Furukawa Electric Co., Ltd.(assignment on the face of the patent)
Sep 03 2008MARUYAMA, HIROMITSUTHE FURUKAWA ELECTRIC CO , LTD ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0215160532 pdf
Sep 03 2008TAGUCHI, SHUZOTHE FURUKAWA ELECTRIC CO , LTD ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0215160532 pdf
Sep 03 2008MORISHIMA, YASUMASATHE FURUKAWA ELECTRIC CO , LTD ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0215160532 pdf
Sep 03 2008ISHIWATA, SHINICHITHE FURUKAWA ELECTRIC CO , LTD ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0215160532 pdf
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