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The ornamental design for a substrate for an electronic circuit, as shown and described.
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The broken line portion of the figure drawings is included to show portions of the article that form no part of the claimed design.
Matsumoto, Manabu, Toyoda, Yasumasa
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Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jun 17 2015 | MATSUMOTO, MANABU | Kabushiki Kaisha Toshiba | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 036325 | /0076 | |
Jun 17 2015 | TOYODA, YASUMASA | Kabushiki Kaisha Toshiba | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 036325 | /0076 | |
Jul 14 2015 | Kabushiki Kaisha Toshiba | (assignment on the face of the patent) | / | |||
Jan 16 2018 | Kabushiki Kaisha Toshiba | Kabushiki Kaisha Toshiba | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 045103 | /0298 | |
Jan 16 2018 | Kabushiki Kaisha Toshiba | TOSHIBA MEMORY CORPORATION | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 045103 | /0298 | |
Oct 01 2019 | TOSHIBA MEMORY CORPORATION | Kioxia Corporation | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 051842 | /0627 |
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