Patent
   D764424
Priority
May 15 2014
Filed
Aug 29 2014
Issued
Aug 23 2016
Expiry
Aug 23 2030
Assg.orig
Entity
unknown
20
32
n/a
The ornamental design for a substrate for an electronic circuit, as shown and described.

FIG. 1 is a perspective view of a substrate for an electronic circuit showing our new design;

FIG. 2 is a rear perspective view thereof,

FIG. 3 is a front elevational view thereof,

FIG. 4 is a rear elevational view thereof,

FIG. 5 is a right side elevational view, a left side elevational view being a mirror image thereof,

FIG. 6 is a top plan view thereof; and,

FIG. 7 is a bottom plan view thereof.

The broken lines shown in the drawings represent portions of the substrate for an electronic circuit that form no part of the claimed design.

Matsumoto, Manabu, Ozawa, Isao

Patent Priority Assignee Title
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Executed onAssignorAssigneeConveyanceFrameReelDoc
Jun 19 2014MATSUMOTO, MANABUKabushiki Kaisha ToshibaASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0336390705 pdf
Jun 19 2014OZAWA, ISAOKabushiki Kaisha ToshibaASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0336390705 pdf
Aug 29 2014Kabushiki Kaisha Toshiba(assignment on the face of the patent)
Mar 02 2018Kabushiki Kaisha ToshibaTOSHIBA MEMORY CORPORATIONASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0451750632 pdf
Oct 01 2019TOSHIBA MEMORY CORPORATIONKioxia CorporationCHANGE OF NAME SEE DOCUMENT FOR DETAILS 0518420627 pdf
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