Patent
   D787457
Priority
Jan 14 2015
Filed
Jul 14 2015
Issued
May 23 2017
Expiry
May 23 2032
Assg.orig
Entity
unknown
19
35
n/a
The ornamental design for a substrate for an electronic circuit, as shown and described.

FIG. 1 is a front, bottom and right side perspective view of a substrate for an electronic circuit, showing our new design;

FIG. 2 is a rear, bottom and left side perspective view thereof;

FIG. 3 is a front view thereof;

FIG. 4 is a rear view thereof;

FIG. 5 is a top view thereof;

FIG. 6 is bottom view thereof;

FIG. 7 is a right side view thereof, the left side being symmetrical;

FIG. 8 is a cross sectional view thereof, taken along line 8-8 in FIG. 3; and,

FIG. 9 is a cross sectional view thereof, taken along line 9-9 in FIG. 3.

The broken line portion of the figure drawings is included to show portions of the article that form no part of the claimed design.

Matsumoto, Manabu, Toyoda, Yasumasa

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Executed onAssignorAssigneeConveyanceFrameReelDoc
Jun 17 2015MATSUMOTO, MANABUKabushiki Kaisha ToshibaASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0360770329 pdf
Jun 17 2015TOYODA, YASUMASAKabushiki Kaisha ToshibaASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0360770329 pdf
Jul 14 2015Kabushiki Kaisha Toshiba(assignment on the face of the patent)
Jan 16 2018Kabushiki Kaisha ToshibaKabushiki Kaisha ToshibaASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0451030298 pdf
Jan 16 2018Kabushiki Kaisha ToshibaTOSHIBA MEMORY CORPORATIONASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0451030298 pdf
Oct 01 2019TOSHIBA MEMORY CORPORATIONKioxia CorporationCHANGE OF NAME SEE DOCUMENT FOR DETAILS 0518420627 pdf
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