Patent
   D673922
Priority
Apr 21 2011
Filed
Jun 10 2011
Issued
Jan 08 2013
Expiry
Jan 08 2027
Assg.orig
Entity
unknown
63
25
n/a
The ornamental design for a portion of a substrate for an electronic circuit, as shown and described.

FIG. 1 is a front, bottom and left side perspective view of a portion of a substrate for an electronic circuit, showing our new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a left side elevational view thereof;

FIG. 4 is a front elevational view thereof;

FIG. 5 is a right side elevational view thereof;

FIG. 6 is a bottom plan view thereof; and,

FIG. 7 is a rear elevational view thereof.

The uneven spaced broken lines define the bounds of the claimed design and form no part thereof. The even spaced broken line showing of the substrate for an electronic circuit is for illustrative purpose only and forms no part of the claimed design.

Ozawa, Isao, Moriai, Takakatsu, Eguchi, Toyokazu

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Executed onAssignorAssigneeConveyanceFrameReelDoc
May 19 2011MORIAI, TAKAKATSUKabushiki Kaisha ToshibaASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0264270220 pdf
May 19 2011OZAWA, ISAOKabushiki Kaisha ToshibaASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0264270220 pdf
May 19 2011EGUCHI, TOYOKAZUKabushiki Kaisha ToshibaASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0264270220 pdf
Jun 10 2011Kabushiki Kaisha Toshiba(assignment on the face of the patent)
Mar 02 2018Kabushiki Kaisha ToshibaTOSHIBA MEMORY CORPORATIONASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0451750632 pdf
Oct 01 2019TOSHIBA MEMORY CORPORATIONKioxia CorporationCHANGE OF NAME SEE DOCUMENT FOR DETAILS 0518420627 pdf
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