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The ornamental design for a semiconductor device, as shown and described.
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FIG. 1 is a front, bottom and right side perspective view of a semiconductor device, showing our new design;
FIG. 2 is a front elevational view thereof;
FIG. 3 is top plan view thereof; a bottom plan view being a mirror image thereof;
FIG. 4 is a right side elevational view thereof; a left side elevational view being a mirror image thereof; and,
FIG. 5 is a rear elevational view thereof.
Ide, Takahiro, Sako, Shigeki, Fukuda, Kazuyoshi, Ootomo, Masahiro
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| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| May 29 2002 | Kabushiki Kaisha Toshiba | (assignment on the face of the patent) | / | |||
| Jun 20 2002 | SAKO, SHIGEKI | Kabushiki Kaisha Toshiba | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 013200 | /0658 | |
| Jun 20 2002 | IDE, TAKAHIRO | Kabushiki Kaisha Toshiba | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 013200 | /0658 | |
| Jun 24 2002 | OOTOMO, MASAHIRO | Kabushiki Kaisha Toshiba | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 013200 | /0658 | |
| Jun 24 2002 | FUKUDA, KAZUYOSHI | Kabushiki Kaisha Toshiba | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 013200 | /0658 |
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