Patent
   D810036
Priority
Nov 08 2016
Filed
Mar 27 2017
Issued
Feb 13 2018
Expiry
Feb 13 2033
Assg.orig
Entity
unknown
13
42
n/a
The ornamental design for a semiconductor module, as shown and described.

FIG. 1 is a front view of a semiconductor module showing our new design;

FIG. 2 is a rear view of the semiconductor module of FIG. 1;

FIG. 3 is a left side view of the semiconductor module of FIG. 1;

FIG. 4 is a right side view of the semiconductor module of FIG. 1;

FIG. 5 is a top view of the semiconductor module of FIG. 1;

FIG. 6 is a bottom view of the semiconductor module of FIG. 1; and,

FIG. 7 is a top, front, right side perspective view of the semiconductor module of FIG. 1.

The broken lines shown in the drawings represent portions of the semiconductor module that form no part of the claimed design.

Takahashi, Hideaki, Taoka, Masahiro, Oose, Tomofumi, Sawayanagi, Satoshi

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Executed onAssignorAssigneeConveyanceFrameReelDoc
Jan 13 2017SAWAYANAGI, SATOSHIFUJI ELECTRIC CO , LTD ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0417770766 pdf
Jan 20 2017TAOKA, MASAHIROFUJI ELECTRIC CO , LTD ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0417770766 pdf
Jan 20 2017OOSE, TOMOFUMIFUJI ELECTRIC CO , LTD ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0417770766 pdf
Jan 20 2017TAKAHASHI, HIDEAKIFUJI ELECTRIC CO , LTD ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0417770766 pdf
Mar 27 2017Fuji Electric Co., Ltd.(assignment on the face of the patent)
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