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Patent
D611013
Priority
Mar 28 2008
Filed
Sep 26 2008
Issued
Mar 02 2010
Expiry
Mar 02 2024
Assg.orig
Entity
unknown
30
13
n/a
The ornamental design for a process tube for manufacturing semiconductor wafers, as shown and described.
FIG. 1 is a perspective view;
FIG. 2 is a front view;
FIG. 3 is a rear view;
FIG. 4 is a left side view and the right side being a mirror image thereof;
FIG. 5 is a plan view and the bottom plan being a mirror image thereof;
FIG. 6 is a sectional view thereof along 6 —6 of the plan view shown in FIG. 5 ;
FIG. 7 is an enlarged sectional view along 7 —7 of the rear view shown in FIG. 3 ; and,
FIG. 8 is a view of process tube for manufacturing semiconductor wafers in use wherein the broken line showing of the environment is for illustrative purposes only and forms no part of the claimed design.
Takahashi, Kiyohiko
Patent
Priority
Assignee
Title
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Tokyo Electron Limited
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Inner tube for process tube for manufacturing semiconductor wafers
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Patent
Priority
Assignee
Title
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Date
Maintenance Fee Events
n/a
Date
Maintenance Schedule
n/a